17 lines
350 B
Python
17 lines
350 B
Python
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from migen.fhdl.std import *
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from migen.fhdl import verilog
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class Example(Module):
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def __init__(self):
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a = Signal(3)
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b = Signal(4)
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c = Signal(5)
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d = Signal(7)
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s1 = c[:3][:2]
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s2 = Cat(a, b)[:6]
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s3 = Cat(s1, s2)[-5:]
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self.comb += s3.eq(0)
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self.comb += d.eq(Cat(d[::-1], Cat(s1[:1], s3[-4:])[:3]))
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print(verilog.convert(Example()))
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