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litex
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Initial import, FHDL basic structure, divider example
2011-12-04 10:44:38 -05:00
__pycache__
*.pyc
Adding .egg-info to the .gitignore
2015-04-14 04:28:55 -04:00
*.egg-info/
gitignore: update
2012-03-08 12:14:19 -05:00
vpi/*.o
vpi/migensim.vpi
examples/*.vcd
doc: switch to sphinx
2012-03-09 11:08:38 -05:00
doc/_build