121 lines
4.9 KiB
Python
121 lines
4.9 KiB
Python
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from migen.fhdl.std import *
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from migen.bank.description import *
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from misoclib.com.litepcie.common import *
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from misoclib.com.litepcie.core.switch.common import *
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from misoclib.com.litepcie.core.switch.request_controller import RequestController
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class Crossbar(Module, AutoCSR):
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def __init__(self, dw, max_pending_requests, with_reordering=False):
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self.dw = dw
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self.max_pending_requests = max_pending_requests
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self.with_reordering = with_reordering
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self.master = MasterInternalPort(dw)
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self.slave = SlaveInternalPort(dw)
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self.phy_master = MasterPort(self.master)
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self.phy_slave = SlavePort(self.slave)
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self.user_masters = []
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self.user_masters_channel = 0
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self.user_slaves = []
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def get_slave_port(self, address_decoder):
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s = SlaveInternalPort(self.dw, address_decoder)
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self.user_slaves.append(s)
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return SlavePort(s)
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def get_master_port(self, write_only=False, read_only=False):
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m = MasterInternalPort(self.dw, self.user_masters_channel, write_only, read_only)
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self.user_masters_channel += 1
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self.user_masters.append(m)
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return MasterPort(m)
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def filter_masters(self, write_only, read_only):
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masters = []
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for m in self.user_masters:
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if m.write_only == write_only and m.read_only == read_only:
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masters.append(m)
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return masters
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def slave_dispatch_arbitrate(self, slaves, slave):
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# dispatch
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s_sources = [s.source for s in slaves]
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s_dispatcher = Dispatcher(slave.source, s_sources, one_hot=True)
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self.submodules += s_dispatcher
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for i, s in enumerate(slaves):
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self.comb += s_dispatcher.sel[i].eq(s.address_decoder(slave.source.adr))
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# arbitrate
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s_sinks = [s.sink for s in slaves]
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s_arbiter = Arbiter(s_sinks, slave.sink)
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self.submodules += s_arbiter
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def master_arbitrate_dispatch(self, masters, master):
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# arbitrate
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m_sinks = [m.sink for m in masters]
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m_arbiter = Arbiter(m_sinks, master.sink)
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self.submodules += m_arbiter
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# dispatch
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m_sources = [m.source for m in masters]
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m_dispatcher = Dispatcher(master.source, m_sources)
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self.submodules += m_dispatcher
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self.comb += m_dispatcher.sel.eq(master.source.channel)
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def do_finalize(self):
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# Slave path
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# Dispatch request to user sources (according to address decoder)
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# Arbitrate completion from user sinks
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if self.user_slaves != []:
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self.slave_dispatch_arbitrate(self.user_slaves, self.slave)
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# Master path
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# Abritrate requests from user sinks
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# Dispatch completion to user sources (according to channel)
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# +-------+
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# reqs---> | RD |
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# cmps<--- | PORTS |---------+
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# +-------+ +---+----+ +----------+
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# |Arb/Disp|-->|Controller|--+
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# +-------+ +---+----+ +----------+ |
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# reqs---> | RW | | |
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# cmps<--- | PORTS |---------+ |
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# +-------+ +---+----+
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# |Arb/Disp|<--> to/from Packetizer/
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# +-------+ +---+----+ Depacketizer
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# reqs---> | WR | +--------+ |
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# cmps<--- | PORTS |-----|Arb/Disp|-----------------+
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# +-------+ +--------+
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#
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# The controller blocks RD requests when the max number of pending
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# requests have been sent (max_pending_requests parameters).
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# To avoid blocking write_only ports when RD requests are blocked,
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# a separate arbitration stage is used.
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if self.user_masters != []:
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masters = []
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# Arbitrate / dispatch read_only / read_write ports
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# and insert controller
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rd_rw_masters = self.filter_masters(False, True)
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rd_rw_masters += self.filter_masters(False, False)
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if rd_rw_masters != []:
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rd_rw_master = MasterInternalPort(self.dw)
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controller = RequestController(self.dw, self.max_pending_requests, self.with_reordering)
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self.submodules += controller
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self.master_arbitrate_dispatch(rd_rw_masters, controller.master_in)
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masters.append(controller.master_out)
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# Arbitrate / dispatch write_only ports
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wr_masters = self.filter_masters(True, False)
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if wr_masters != []:
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wr_master = MasterInternalPort(self.dw)
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self.master_arbitrate_dispatch(wr_masters, wr_master)
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masters.append(wr_master)
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# Final Arbitrate / dispatch stage
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self.master_arbitrate_dispatch(masters, self.master)
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