42 lines
1.3 KiB
Plaintext
42 lines
1.3 KiB
Plaintext
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/ / (_) /____ | |/_/
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/ /__/ / __/ -_)> <
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/____/_/\__/\__/_/|_|
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Build your hardware, easily!
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Copyright 2015 Enjoy-Digital
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(based on Migen/MiSoC technologies)
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[> Intro
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---------
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LiteX is a fork of Migen/MiSoC for our own needs at Enjoy-Digital. It provides
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a single python package and add some specific features to design our FPGA cores,
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build a SoC with or or load/flash it to the hardware.
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The structure of LiteX is kept close to Migen/MiSoC to enable collaboration
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between projects.
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[> License
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-----------
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LiteX is copyright (c) 2015 Enjoy-Digital.
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Since it is based on Migen/MiSoC, see gen/MIGEN_LICENSE and soc/MISOC_LICENSE or
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git history to get correct ownership of files.
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[> Sub-packages
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-----------
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gen:
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Provides tools and simple modules to generate HDL.
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build:
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Provides tools to build FPGA bitstreams (interface to vendor toolchains) and to
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simulate HDL code or full SoCs.
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soc:
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Provides definitions/modules to build cores (bus, bank, flow), cores and tools
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to build a SoC from such cores.
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boards:
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Provides platforms and targets for the supported boards.
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[> Contact
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E-mail: florent [AT] enjoy-digital.fr
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