2020-08-23 09:40:21 -04:00
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#
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# This file is part of LiteX.
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#
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# Copyright (c) 2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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2019-07-05 12:30:34 -04:00
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import unittest
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from migen import *
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2019-10-01 15:30:14 -04:00
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from litex.soc.cores.icap import ICAP, ICAPBitstream
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2019-07-05 12:30:34 -04:00
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class TestICAP(unittest.TestCase):
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2019-10-01 15:30:14 -04:00
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def test_icap_command_reload(self):
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def generator(dut):
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2020-10-07 06:36:08 -04:00
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yield dut.addr.eq(0x4)
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yield dut.data.eq(0xf)
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for i in range(16):
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yield
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yield dut.send.eq(1)
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2019-07-05 12:30:34 -04:00
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yield
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yield dut.send.eq(0)
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2019-07-05 12:30:34 -04:00
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for i in range(256):
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yield
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2020-10-07 06:36:08 -04:00
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dut = ICAP(with_csr=False, simulation=True)
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clocks = {"sys": 10, "icap":20}
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2019-07-05 12:30:34 -04:00
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run_simulation(dut, generator(dut), clocks, vcd_name="icap.vcd")
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2019-10-01 15:30:14 -04:00
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def test_icap_bitstream_syntax(self):
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dut = ICAPBitstream(simulation=True)
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