99 lines
3.5 KiB
Python
99 lines
3.5 KiB
Python
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from migen.bus import wishbone
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from migen.bank.description import *
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from migen.genlib.io import CRG
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from migen.genlib.misc import timeline
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from misoclib.soc import SoC
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from misoclib.tools.litescope.common import *
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from misoclib.tools.litescope.bridge.uart2wb import LiteScopeUART2WB
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from misoclib.com.litepcie.phy.s7pciephy import S7PCIEPHY
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from misoclib.com.litepcie.core import Endpoint
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from misoclib.com.litepcie.core.irq.interrupt_controller import InterruptController
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from misoclib.com.litepcie.frontend.dma import DMA
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from misoclib.com.litepcie.frontend.bridge.wishbone import WishboneBridge
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class _CRG(Module, AutoCSR):
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def __init__(self, platform):
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self.clock_domains.cd_sys = ClockDomain("sys")
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self.clock_domains.cd_clk125 = ClockDomain("clk125")
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# soft reset generaton
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self._soft_rst = CSR()
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soft_rst = Signal()
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# trigger soft reset 1us after CSR access to terminate
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# Wishbone access when reseting from PCIe
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self.sync += [
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timeline(self._soft_rst.re & self._soft_rst.r, [(125, [soft_rst.eq(1)])]),
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]
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# sys_clk / sys_rst (from PCIe)
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self.comb += self.cd_sys.clk.eq(self.cd_clk125.clk)
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self.specials += AsyncResetSynchronizer(self.cd_sys, self.cd_clk125.rst | soft_rst)
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# scratch register
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self._scratch = CSR(32)
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self.sync += If(self._scratch.re, self._scratch.w.eq(self._scratch.r))
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class PCIeDMASoC(SoC, AutoCSR):
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default_platform = "kc705"
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csr_map = {
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"crg": 16,
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"pcie_phy": 17,
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"dma": 18,
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"irq_controller": 19
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}
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csr_map.update(SoC.csr_map)
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interrupt_map = {
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"dma_writer": 0,
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"dma_reader": 1
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}
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interrupt_map.update(SoC.interrupt_map)
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mem_map = {
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"csr": 0x00000000, # (shadow @0x80000000)
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}
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mem_map.update(SoC.csr_map)
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def __init__(self, platform, with_uart_bridge=True):
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clk_freq = 125*1000000
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SoC.__init__(self, platform, clk_freq,
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cpu_type="none",
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shadow_address=0x00000000,
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with_csr=True, csr_data_width=32,
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with_uart=False,
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with_identifier=True,
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with_timer=False
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)
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self.submodules.crg = _CRG(platform)
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# PCIe endpoint
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self.submodules.pcie_phy = S7PCIEPHY(platform, link_width=2)
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self.submodules.pcie_endpoint = Endpoint(self.pcie_phy, with_reordering=True)
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# PCIe Wishbone bridge
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self.add_cpu_or_bridge(WishboneBridge(self.pcie_endpoint, lambda a: 1))
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self.add_wb_master(self.cpu_or_bridge.wishbone)
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# PCIe DMA
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self.submodules.dma = DMA(self.pcie_phy, self.pcie_endpoint, with_loopback=True)
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self.dma.source.connect(self.dma.sink)
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if with_uart_bridge:
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self.submodules.uart_bridge = LiteScopeUART2WB(platform.request("serial"), clk_freq, baudrate=115200)
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self.add_wb_master(self.uart_bridge.wishbone)
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# IRQs
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self.submodules.irq_controller = InterruptController()
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self.comb += self.irq_controller.source.connect(self.pcie_phy.interrupt)
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self.interrupts = {
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"dma_writer": self.dma.writer.table.irq,
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"dma_reader": self.dma.reader.table.irq
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}
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for k, v in sorted(self.interrupts.items()):
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self.comb += self.irq_controller.irqs[self.interrupt_map[k]].eq(v)
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default_subtarget = PCIeDMASoC
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