23 lines
736 B
Python
23 lines
736 B
Python
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from migen.fhdl import convtools, verilog, autofragment
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from migen.bus import wishbone, csr, wishbone2csr
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from milkymist import lm32, norflash, uart
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import constraints
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def Get():
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cpu0 = lm32.Inst()
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norflash0 = norflash.Inst(25, 12)
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wishbone2csr0 = wishbone2csr.Inst()
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wishbonecon0 = wishbone.InterconnectShared(
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[cpu0.ibus, cpu0.dbus],
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[(0, norflash0.bus), (3, wishbone2csr0.wishbone)],
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register=True,
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offset=1)
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uart0 = uart.Inst(0, 50*1000*1000, baud=115200)
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csrcon0 = csr.Interconnect(wishbone2csr0.csr, [uart0.bus])
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frag = autofragment.FromLocal()
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vns = convtools.Namespace()
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src_verilog = verilog.Convert(frag, name="soc", ns=vns)
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src_ucf = constraints.Get(vns, norflash0, uart0)
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return (src_verilog, src_ucf)
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