38 lines
1.3 KiB
Python
38 lines
1.3 KiB
Python
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from migen.fhdl import verilog
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from migen.fhdl.std import *
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from migen.genlib.mhamgen import HammingGenerator, HammingChecker
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# Instantiates Hamming code generator and checker modules back
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# to back. Also creates an intermediate bus between generator
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# and checker and injects a single-bit error on the bus, to
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# demonstrate the correction.
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class gen_check(Module):
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def __init__(self, width=8):
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# Save module parameters and instantiate generator and checker
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self.width = width
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hg = HammingGenerator(self.width)
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hc = HammingChecker(self.width, correct=True)
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self.submodules += hg
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self.submodules += hc
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# Create the intermediate bus and inject a single-bit error on
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# the bus. Position of the error bit is controllable by the
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# error_bit input.
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data = Signal(width)
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error_bit = Signal(bits_for(width))
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self.comb += data.eq(hg.data_in ^ (1 << error_bit))
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self.comb += hc.code_in.eq(hg.code_out)
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self.comb += hc.data_in.eq(data)
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# Call out I/O necessary for testing the generator/checker
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self.io = set()
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self.io.add(hg.data_in)
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self.io.add(hc.enable)
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self.io.add(error_bit)
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self.io.add(hc.code_out)
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self.io.add(hc.data_out)
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gc = gen_check()
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print(verilog.convert(gc, gc.io, name="gen_check"))
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