83 lines
2.9 KiB
Python
83 lines
2.9 KiB
Python
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#
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# This file is part of LiteX.
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#
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# Copyright (c) 2022 Wolfgang Nagele <mail@wnagele.com>
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# SPDX-License-Identifier: BSD-2-Clause
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import unittest
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from migen import *
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from litex.soc.cores.led import WS2812
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TEST_CLK_FREQS = (20e6, 16e6, 15e6, 10e6)
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class TestWS2812(unittest.TestCase):
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def generator(self, dut, led_signal, led_data, sys_clk_freq, iterations):
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error_margin = 0.15e-6 # defined in datasheet
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# cap on how long a sequence will be evaluated
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max_cycles_per_seq = int(dut.trst * sys_clk_freq * 2)
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# initial reset
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rst_cycles = 0
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for _ in range(max_cycles_per_seq):
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if (yield led_signal) != 0:
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break
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rst_cycles += 1
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yield
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rst_time = rst_cycles / sys_clk_freq
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assert rst_time >= dut.trst
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length = len(led_data)
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for _ in range(iterations):
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for i_num, num in enumerate(led_data, start = 1):
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for idx_bit, bit in enumerate(TestWS2812.to_bits(num), start = 1):
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exp_high, exp_low = (dut.t0h, dut.t0l) if bit == 0 else (dut.t1h, dut.t1l)
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# end of chain reset
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if i_num == length and idx_bit == 24:
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exp_low += dut.trst
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high_cycles = 0
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for _ in range(max_cycles_per_seq):
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if (yield led_signal) != 1:
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break
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high_cycles += 1
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yield
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high_time = high_cycles / sys_clk_freq
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assert high_time >= exp_high - error_margin
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assert high_time <= exp_high + error_margin
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low_cycles = 0
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for _ in range(max_cycles_per_seq):
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if (yield led_signal) != 0:
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break
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low_cycles += 1
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yield
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low_time = low_cycles / sys_clk_freq
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assert low_time >= exp_low - error_margin
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assert low_time <= exp_low + error_margin
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def to_bits(num, length = 24):
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return ( int(x) for x in bin(num)[2:].zfill(length) )
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def run_test(self, hardware_revision, sys_clk_freq):
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led_signal = Signal()
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led_data = [ 0x100000, 0x200000, 0x300000, 0x400000, 0x500000, 0x600000, 0x700000, 0x800000, 0x900000 ]
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iterations = 3
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dut = WS2812(led_signal, len(led_data), sys_clk_freq, hardware_revision = hardware_revision, test_data = led_data)
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run_simulation(dut, self.generator(dut, led_signal, led_data, sys_clk_freq, iterations))
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def test_WS2812_old(self):
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for sys_clk_freq in TEST_CLK_FREQS:
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self.run_test("old", sys_clk_freq)
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def test_WS2812_new(self):
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for sys_clk_freq in TEST_CLK_FREQS:
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self.run_test("new", sys_clk_freq)
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