2014-09-23 17:03:32 -04:00
|
|
|
from migen.fhdl.std import *
|
2014-09-24 08:28:52 -04:00
|
|
|
from migen.flow.actor import Sink, Source
|
2014-09-23 17:03:32 -04:00
|
|
|
|
|
|
|
from lib.sata.k7sataphy.std import *
|
|
|
|
from lib.sata.k7sataphy.gtx import GTXE2_CHANNEL
|
|
|
|
from lib.sata.k7sataphy.clocking import K7SATAPHYClocking
|
2014-09-24 08:28:52 -04:00
|
|
|
from lib.sata.k7sataphy.ctrl import K7SATAPHYHostCtrl, K7SATAPHYDeviceCtrl
|
2014-09-23 17:03:32 -04:00
|
|
|
|
|
|
|
class K7SATAPHY(Module):
|
2014-09-24 07:56:32 -04:00
|
|
|
def __init__(self, pads, host=True):
|
|
|
|
self.sink = Sink([("d", 32)], True)
|
|
|
|
self.source = Source([("d", 32)], True)
|
2014-09-23 17:03:32 -04:00
|
|
|
|
|
|
|
self.submodules.gtx = GTXE2_CHANNEL(pads, "SATA3")
|
|
|
|
self.submodules.clocking = K7SATAPHYClocking(pads, self.gtx)
|
2014-09-24 07:56:32 -04:00
|
|
|
if host:
|
|
|
|
self.submodules.ctrl = K7SATAPHYHostCtrl(self.gtx)
|
|
|
|
else:
|
|
|
|
self.submodules.ctrl = K7SATAPHYDeviceCtrl(self.gtx)
|
|
|
|
self.comb += [
|
|
|
|
If(self.ctrl.link_up,
|
|
|
|
self.gtx.sink.stb.eq(self.sink.stb),
|
2014-09-24 08:28:52 -04:00
|
|
|
self.gtx.sink.data.eq(self.sink.d),
|
2014-09-24 07:56:32 -04:00
|
|
|
self.gtx.sink.charisk.eq(0),
|
|
|
|
self.sink.ack.eq(self.gtx.sink.ack),
|
|
|
|
).Else(
|
|
|
|
self.gtx.sink.stb.eq(1),
|
|
|
|
self.gtx.sink.data.eq(self.ctrl.txdata),
|
2014-09-24 08:28:52 -04:00
|
|
|
self.gtx.sink.charisk.eq(self.ctrl.txcharisk)
|
|
|
|
),
|
|
|
|
self.source.stb.eq(self.gtx.source.stb),
|
|
|
|
self.source.payload.eq(self.gtx.source.payload),
|
|
|
|
self.gtx.source.ack.eq(self.source.ack),
|
|
|
|
self.ctrl.rxdata.eq(self.gtx.source.data)
|
2014-09-24 07:56:32 -04:00
|
|
|
]
|