55 lines
1.1 KiB
Python
55 lines
1.1 KiB
Python
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from subprocess import check_output
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from migen.fhdl.std import *
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from lib.sata.std import *
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from lib.sata.link.scrambler import *
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def check(ref, res):
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shift = 0
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while((ref[0] != res[0]) and (len(res)>1)):
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res.pop(0)
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shift += 1
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length = min(len(ref), len(res))
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errors = 0
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for i in range(length):
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if ref.pop(0) != res.pop(0):
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errors += 1
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return shift, length, errors
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class TB(Module):
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def __init__(self):
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self.submodules.scrambler = SATAScrambler()
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def gen_simulation(self, selfp):
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# init CRC
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selfp.scrambler.ce = 1
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selfp.scrambler.reset = 1
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yield
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selfp.scrambler.reset = 0
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# get C code results
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ref = []
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f = open("scrambler_ref", "r")
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for l in f:
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ref.append(int(l, 16))
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f.close()
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# log results
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yield
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res = []
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for i in range(256):
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res.append(selfp.scrambler.value)
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yield
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for e in res:
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print("%08x" %e)
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# check results
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s, l, e = check(ref, res)
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print("shift "+ str(s) + " / length " + str(l) + " / errors " + str(e))
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if __name__ == "__main__":
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from migen.sim.generic import run_simulation
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run_simulation(TB(), ncycles=1000, vcd_name="my.vcd", keep_files=True)
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