2015-02-26 14:31:01 -05:00
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import os
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2014-05-14 04:24:56 -04:00
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from migen.fhdl.std import *
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from migen.bus import wishbone
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class MOR1KX(Module):
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2015-02-26 14:31:01 -05:00
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def __init__(self, platform, reset_pc):
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2014-05-14 04:24:56 -04:00
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self.ibus = i = wishbone.Interface()
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self.dbus = d = wishbone.Interface()
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self.interrupt = Signal(32)
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###
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i_adr_o = Signal(32)
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d_adr_o = Signal(32)
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self.specials += Instance("mor1kx",
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p_FEATURE_INSTRUCTIONCACHE="ENABLED",
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p_OPTION_ICACHE_BLOCK_WIDTH=4,
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p_OPTION_ICACHE_SET_WIDTH=8,
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p_OPTION_ICACHE_WAYS=1,
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p_OPTION_ICACHE_LIMIT_WIDTH=31,
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p_FEATURE_DATACACHE="ENABLED",
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p_OPTION_DCACHE_BLOCK_WIDTH=4,
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p_OPTION_DCACHE_SET_WIDTH=8,
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p_OPTION_DCACHE_WAYS=1,
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p_OPTION_DCACHE_LIMIT_WIDTH=31,
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p_FEATURE_TIMER="NONE",
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p_OPTION_PIC_TRIGGER="LEVEL",
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p_FEATURE_SYSCALL="NONE",
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p_FEATURE_TRAP="NONE",
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p_FEATURE_RANGE="NONE",
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p_FEATURE_OVERFLOW="NONE",
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p_FEATURE_ADDC="NONE",
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p_FEATURE_CMOV="NONE",
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p_FEATURE_FFL1="NONE",
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p_OPTION_CPU0="CAPPUCCINO",
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p_OPTION_RESET_PC=reset_pc,
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p_IBUS_WB_TYPE="B3_REGISTERED_FEEDBACK",
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p_DBUS_WB_TYPE="B3_REGISTERED_FEEDBACK",
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i_clk=ClockSignal(),
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i_rst=ResetSignal(),
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i_irq_i=self.interrupt,
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o_iwbm_adr_o=i_adr_o,
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o_iwbm_dat_o=i.dat_w,
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o_iwbm_sel_o=i.sel,
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o_iwbm_cyc_o=i.cyc,
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o_iwbm_stb_o=i.stb,
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o_iwbm_we_o=i.we,
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o_iwbm_cti_o=i.cti,
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o_iwbm_bte_o=i.bte,
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i_iwbm_dat_i=i.dat_r,
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i_iwbm_ack_i=i.ack,
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i_iwbm_err_i=i.err,
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i_iwbm_rty_i=0,
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o_dwbm_adr_o=d_adr_o,
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o_dwbm_dat_o=d.dat_w,
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o_dwbm_sel_o=d.sel,
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o_dwbm_cyc_o=d.cyc,
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o_dwbm_stb_o=d.stb,
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o_dwbm_we_o=d.we,
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o_dwbm_cti_o=d.cti,
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o_dwbm_bte_o=d.bte,
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i_dwbm_dat_i=d.dat_r,
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i_dwbm_ack_i=d.ack,
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i_dwbm_err_i=d.err,
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i_dwbm_rty_i=0)
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self.comb += [
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self.ibus.adr.eq(i_adr_o[2:]),
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self.dbus.adr.eq(d_adr_o[2:])
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]
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2015-02-26 14:31:01 -05:00
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# add Verilog sources
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platform.add_source_dir(os.path.join("extcores", "mor1kx", "submodule", "rtl", "verilog"))
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