36 lines
887 B
Tcl
36 lines
887 B
Tcl
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set HDL_TOOLTYPE SYNTHESIS
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set HDL_TOOLNAME QuartusII
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set HDL_PUTS puts
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set HDL_MSG_FORMAT "********** %s **********"
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proc hdl_tool_library {lib_list} {
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}
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proc hdl_tool_compile {format version incdirs library define files behavioral} {
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#if {[llength $incdirs]} {
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# error "-incdir not yet supported"
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#}
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switch $format {
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"vhdl" {
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foreach f $files {
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set_global_assignment -name VHDL_FILE $f -library $library
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}
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}
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"verilog" {
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foreach d $define {
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set_global_assignment -name VERILOG_MACRO $d
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}
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foreach f $files {
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set_global_assignment -name VERILOG_FILE $f -library $library
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}
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}
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}
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}
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if { [catch { puts "Quartus hdl_common script" } ] } {
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# Disable puts for Quartus (doesn't work with the GUI since no stdout channel)
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proc hdl_puts { msg } {
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}
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}
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