56 lines
1.4 KiB
Python
56 lines
1.4 KiB
Python
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from migen.fhdl.structure import *
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from migen.fhdl import verilog, autofragment
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from migen.bus import csr
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from migen.bus.transactions import *
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from migen.bank import description, csrgen
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from migen.bank.description import *
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import sys
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sys.path.append("../../../")
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from migScope import trigger, recorder, migIo
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import spi2Csr
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from spi2Csr.tools.uart2Spi import *
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#==============================================================================
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# P A R A M E T E R S
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#==============================================================================
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# Bus Width
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trig_width = 16
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dat_width = 16
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# Record Size
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record_size = 1024
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# Csr Addr
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MIGIO0_ADDR = 0x0000
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TRIGGER_ADDR = 0x0200
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RECORDER_ADDR = 0x0400
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# MigScope Configuration
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# migIo
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migIo0 = migIo.MigIo(MIGIO0_ADDR, 8, "IO")
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# Trigger
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term0 = trigger.Term(trig_width)
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trigger0 = trigger.Trigger(TRIGGER_ADDR, trig_width, dat_width, [term0])
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# Recorder
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recorder0 = recorder.Recorder(RECORDER_ADDR, dat_width, record_size)
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#==============================================================================
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# T E S T M I G I O
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#==============================================================================
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csr = Uart2Spi(1,115200)
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print("1) Write Led Reg")
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for i in range(10):
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csr.write(MIGIO0_ADDR + 0,0xA5)
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time.sleep(0.1)
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csr.write(MIGIO0_ADDR + 0,0x5A)
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time.sleep(0.1)
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print("2) Read Switch Reg")
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print(csr.read(MIGIO0_ADDR + 1))
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