litex/migScope/migIo.py

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from migen.fhdl.structure import *
from migen.bus import csr
from migen.bank import description, csrgen
from migen.bank.description import *
class MigIo:
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def __init__(self,address, width, mode = "IO"):
self.address = address
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self.width = width
self.mode = mode
if "I" in self.mode:
self.i = Signal(BV(self.width))
self.ireg = description.RegisterField("i", self.width, READ_ONLY, WRITE_ONLY)
self.ireg.field.w.name_override = "inputs"
if "O" in self.mode:
self.o = Signal(BV(self.width))
self.oreg = description.RegisterField("o", self.width)
self.oreg.field.r.name_override = "ouptuts"
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self.bank = csrgen.Bank([self.oreg, self.ireg], address=self.address)
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def get_fragment(self):
comb = []
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if "I" in self.mode:
comb += [self.ireg.field.w.eq(self.i)]
if "O" in self.mode:
comb += [self.o.eq(self.oreg.field.r)]
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return Fragment(comb=comb) + self.bank.get_fragment()