2013-02-22 08:28:05 -05:00
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from migen.fhdl.structure import *
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2013-09-21 07:04:07 -04:00
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from migen.flow.actor import *
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from migen.flow.network import *
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2013-02-22 08:28:05 -05:00
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from migen.bus import csr
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from migen.bank import description, csrgen
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from migen.bank.description import *
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2013-09-21 07:04:07 -04:00
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class MiLa(Module, AutoCSR):
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def __init__(self, trigger, recorder):
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2013-02-22 08:28:05 -05:00
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self.trigger = trigger
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self.recorder = recorder
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2013-03-21 07:23:44 -04:00
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2013-09-21 07:04:07 -04:00
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self.sink = trigger.sink
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self.submodules += trigger, recorder
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2013-03-21 07:23:44 -04:00
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2013-09-21 07:04:07 -04:00
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self.comb +=[
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recorder.sink.stb.eq(trigger.source.stb),
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2013-02-22 08:28:05 -05:00
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2013-09-21 07:04:07 -04:00
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recorder.sink.payload.hit.eq(trigger.source.payload.hit),
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trigger.source.ack.eq(recorder.sink.ack)
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2013-02-22 08:28:05 -05:00
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]
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2013-09-21 07:04:07 -04:00
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# Todo; Insert configurable delay to support pipelined
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# triggers elements
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self.comb +=[
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recorder.sink.payload.d.eq(self.sink.payload.d),
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]
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