2012-02-17 05:04:44 -05:00
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from migen.fhdl.structure import *
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from migen.bus import dfi
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class S6DDRPHY:
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2012-02-19 12:43:42 -05:00
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def __init__(self, a, ba, d):
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2012-02-17 05:04:44 -05:00
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ins = []
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outs = []
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inouts = []
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for name in [
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2012-02-20 17:55:20 -05:00
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"clk2x_270",
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2012-02-19 12:43:42 -05:00
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"clk4x_wr",
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"clk4x_wr_strb",
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"clk4x_rd",
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"clk4x_rd_strb"
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2012-02-17 05:04:44 -05:00
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]:
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s = Signal(name=name)
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setattr(self, name, s)
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ins.append((name, s))
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self._sd_pins = []
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for name, width, l in [
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("sd_clk_out_p", 1, outs),
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("sd_clk_out_n", 1, outs),
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("sd_a", a, outs),
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("sd_ba", ba, outs),
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("sd_cs_n", 1, outs),
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("sd_cke", 1, outs),
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("sd_ras_n", 1, outs),
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("sd_cas_n", 1, outs),
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("sd_we_n", 1, outs),
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2012-02-19 12:43:42 -05:00
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("sd_dq", d//2, inouts),
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("sd_dm", d//16, outs),
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("sd_dqs", d//16, inouts)
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2012-02-17 05:04:44 -05:00
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]:
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s = Signal(BV(width), name=name)
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setattr(self, name, s)
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l.append((name, s))
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self._sd_pins.append(s)
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2012-02-19 12:43:42 -05:00
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self.dfi = dfi.Interface(a, ba, d, 2)
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2012-02-17 05:04:44 -05:00
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ins += self.dfi.get_standard_names(True, False)
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outs += self.dfi.get_standard_names(False, True)
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2012-02-19 12:43:42 -05:00
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self._inst = Instance("s6ddrphy",
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2012-02-17 05:04:44 -05:00
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outs,
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ins,
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inouts,
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[
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("NUM_AD", a),
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("NUM_BA", ba),
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2012-02-19 12:43:42 -05:00
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("NUM_D", d)
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2012-02-17 05:04:44 -05:00
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],
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2012-02-19 12:43:42 -05:00
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clkport="sys_clk")
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2012-02-17 05:04:44 -05:00
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def get_fragment(self):
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2012-02-19 12:43:42 -05:00
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return Fragment(instances=[self._inst], pads=set(self._sd_pins))
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