47 lines
1.5 KiB
Python
47 lines
1.5 KiB
Python
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from migen.bank.description import *
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from migen.genlib.io import CRG
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from migen.actorlib.fifo import SyncFIFO
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from misoclib.soc import SoC
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from misoclib.com.liteusb.common import *
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from misoclib.com.liteusb.phy.ft245 import FT245PHY
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from misoclib.com.liteusb.core import LiteUSBCore
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from misoclib.com.liteusb.frontend.wishbone import LiteUSBWishboneBridge
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from misoclib.com.gpio import GPIOOut
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class LiteUSBSoC(SoC, AutoCSR):
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csr_map = {}
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csr_map.update(SoC.csr_map)
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usb_map = {
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"bridge": 0
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}
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def __init__(self, platform):
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clk_freq = int((1/(platform.default_clk_period))*1000000000)
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SoC.__init__(self, platform, clk_freq,
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cpu_type="none",
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with_csr=True, csr_data_width=32,
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with_uart=False,
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with_identifier=True,
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with_timer=False
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)
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self.submodules.crg = CRG(platform.request(platform.default_clk_name))
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self.submodules.usb_phy = FT245PHY(platform.request("usb_fifo"), self.clk_freq)
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self.submodules.usb_core = LiteUSBCore(self.usb_phy, self.clk_freq, with_crc=False)
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# Wishbone Bridge
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usb_bridge_port = self.usb_core.crossbar.get_port(self.usb_map["bridge"])
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self.add_cpu_or_bridge(LiteUSBWishboneBridge(usb_bridge_port, self.clk_freq))
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self.add_wb_master(self.cpu_or_bridge.wishbone)
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# Leds
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leds = Cat(iter([platform.request("user_led", i) for i in range(8)]))
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self.submodules.leds = GPIOOut(leds)
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default_subtarget = LiteUSBSoC
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