2012-08-12 08:38:49 -04:00
|
|
|
[> migScope
|
|
|
|
|
------------
|
|
|
|
|
|
2013-01-21 16:35:22 -05:00
|
|
|
This is a small Logic Analyser to be embedded in a Fpga design to debug internal
|
|
|
|
|
or external signals.
|
2012-08-12 08:38:49 -04:00
|
|
|
|
|
|
|
|
[> Status:
|
2013-01-21 16:35:22 -05:00
|
|
|
Early development phase
|
|
|
|
|
|
|
|
|
|
Simulation:
|
|
|
|
|
-tb_spi2Csr : Test Spi <--> Csr Bridge : [Ok]
|
|
|
|
|
-tb_TriggerCsr : Test Trigger with Csr : [Ok]
|
|
|
|
|
-tb_RecorderCsr : Test Recorder with Csr : [Ok]
|
|
|
|
|
-tb_MigScope : Global Test with Csr : [Ok]
|
|
|
|
|
|
|
|
|
|
Example Design:
|
|
|
|
|
-de0_nano : Generate Signals in FPGA and probe them with migScope : [Ok]
|
|
|
|
|
Toolchain [Ok]
|
|
|
|
|
-de1 : Generate Signals in FPGA and probe them with migScope : [Ok]
|
|
|
|
|
Toolchain [Ok]
|
|
|
|
|
- test_MigIo : Led & Switch Test controlled by Python [Ok]
|
|
|
|
|
- test_MigLa : Logic Analyzer controlled by Python [Ok]
|
2012-09-09 17:46:26 -04:00
|
|
|
|
2012-08-12 08:38:49 -04:00
|
|
|
[> Contact
|
|
|
|
|
E-mail: florent@enjoy-digital.fr
|
