litex/examples/dataflow_dma.py

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import networkx as nx
from migen.fhdl import verilog
from migen.flow.ala import *
from migen.flow.network import *
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from migen.actorlib import dma_wishbone, control
L = [
("x", BV(10), 8),
("y", BV(10), 8),
("level2", [
("a", BV(5), 32),
("b", BV(5), 16)
])
]
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adrgen = control.For(10)
reader = dma_wishbone.Reader(L)
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g = nx.MultiDiGraph()
add_connection(g, adrgen, reader)
comp = CompositeActor(g)
frag = comp.get_fragment()
ios = set(reader.bus.signals())
ios.add(comp.busy)
print(verilog.convert(frag, ios=ios))