91 lines
2.1 KiB
Python
91 lines
2.1 KiB
Python
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from migen.fhdl.structure import *
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from migen.fhdl import verilog, autofragment
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from migen.bus import csr
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from migen.bus.transactions import *
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from migen.bank import description, csrgen
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from migen.bank.description import *
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import sys
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sys.path.append("../../../")
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from migScope import trigger, recorder, migIo
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from migScope.tools.truthtable import *
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from migScope.tools.vcd import *
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import spi2Csr
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from spi2Csr.tools.uart2Spi import *
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#==============================================================================
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# P A R A M E T E R S
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#==============================================================================
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# Bus Width
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trig_width = 16
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dat_width = 16
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# Record Size
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record_size = 4096
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# Csr Addr
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MIGIO0_ADDR = 0x0000
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TRIGGER_ADDR = 0x0200
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RECORDER_ADDR = 0x0400
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csr = Uart2Spi(1,115200)
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# MigScope Configuration
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# migIo
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migIo0 = migIo.MigIo(MIGIO0_ADDR, 8, "IO",csr)
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# Trigger
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term0 = trigger.Term(trig_width)
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trigger0 = trigger.Trigger(TRIGGER_ADDR, trig_width, dat_width, [term0], csr)
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# Recorder
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recorder0 = recorder.Recorder(RECORDER_ADDR, dat_width, record_size, csr)
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#==============================================================================
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# T E S T M I G L A
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#==============================================================================
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dat_vcd = []
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recorder0.size(1024)
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def capture():
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global trigger0
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global recorder0
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global dat_vcd
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sum_tt = gen_truth_table("term0")
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trigger0.sum.write(sum_tt)
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recorder0.reset()
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recorder0.offset(0)
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recorder0.arm()
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print("-Recorder [Armed]")
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print("-Waiting Trigger...", end = ' ')
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while(not recorder0.is_done()):
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time.sleep(0.1)
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print("[Done]")
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print("-Receiving Data...", end = ' ')
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sys.stdout.flush()
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dat_vcd += recorder0.read(1024)
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print("[Done]")
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print("Capturing Ramp..")
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print("----------------------")
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term0.write(0x0000)
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csr.write(0x0000, 0)
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capture()
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print("Capturing Square..")
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print("----------------------")
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term0.write(0x0000)
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csr.write(0x0000, 1)
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capture()
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print("Capturing Sinus..")
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print("----------------------")
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term0.write(0x0080)
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csr.write(0x0000, 2)
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capture()
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myvcd = Vcd()
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myvcd.add(Var("wire", 16, "trig_dat", dat_vcd))
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myvcd.write("test_MigLa.vcd")
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