litex/targets/core.py

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from migen.genlib.resetsync import AsyncResetSynchronizer
from litesata.common import *
from litesata.phy import LiteSATAPHY
from litesata import LiteSATA
class LiteSATACore(Module):
default_platform = "verilog_backend"
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def __init__(self, platform, clk_freq=166*1000000, nports=4):
self.clk_freq = clk_freq
# SATA PHY/Core/Frontend
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self.submodules.sata_phy = LiteSATAPHY(platform.device, platform.request("sata"), "sata_gen2", clk_freq)
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self.submodules.sata = LiteSATA(self.sata_phy, with_bist=True)
# Get user ports from crossbar
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self.user_ports = self.sata.crossbar.get_ports(nports)
def get_ios(self):
ios = set()
# Transceiver
for e in dir(self.sata_phy.pads):
obj = getattr(self.sata_phy.pads, e)
if isinstance(obj, Signal):
ios = ios.union({obj})
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# Status
ios = ios.union({
self.sata_phy.crg.ready,
self.sata_phy.ctrl.ready
})
# BIST
if hasattr(self.sata, "bist"):
for bist_unit in ["generator", "checker"]:
for signal in ["start", "sector", "count", "random", "done", "aborted", "errors"]:
ios = ios.union({getattr(getattr(self.sata.bist, bist_unit), signal)})
ios = ios.union({
self.sata.bist.identify.start,
self.sata.bist.identify.done,
self.sata.bist.identify.source.stb,
self.sata.bist.identify.source.data,
self.sata.bist.identify.source.ack
})
# User ports
def _iter_layout(layout):
for e in layout:
if isinstance(e[1], list):
yield from _iter_layout(e[1])
else:
yield e
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for port in self.user_ports:
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for endpoint in [port.sink, port.source]:
for e in _iter_layout(endpoint.layout):
obj = getattr(endpoint, e[0])
ios = ios.union({obj})
return ios
default_subtarget = LiteSATACore