litex/examples/sim/memory.py

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# Copyright (C) 2012 Vermeer Manufacturing Co.
# License: GPLv3 with additional permissions (see README).
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from migen.fhdl.structure import *
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from migen.sim.generic import Simulator
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from migen.sim.icarus import Runner
class Mem:
def __init__(self):
self.a = Signal(BV(12))
self.d = Signal(BV(16))
p = MemoryPort(self.a, self.d)
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# Initialize the beginning of the memory with integers
# from 0 to 19.
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self.mem = Memory(16, 2**12, p, init=list(range(20)))
def do_simulation(self, s):
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# Read the memory. Use the cycle counter as address.
value = s.rd(self.mem, s.cycle_counter)
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# Print the result. Output is:
# 0
# 1
# 2
# ...
print(value)
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# Demonstrate how to interrupt the simulator.
if value == 10:
s.interrupt = True
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def get_fragment(self):
return Fragment(memories=[self.mem], sim=[self.do_simulation])
def main():
dut = Mem()
sim = Simulator(dut.get_fragment(), Runner())
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# No need for a cycle limit here, we use sim.interrupt instead.
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sim.run()
main()