25 lines
523 B
Python
25 lines
523 B
Python
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import unittest
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from migen.fhdl.std import *
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from migen.sim.generic import Simulator
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from migen.fhdl import verilog
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class SimBench(Module):
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callback = None
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def do_simulation(self, s):
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if self.callback is not None:
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return self.callback(self, s)
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class SimCase(unittest.TestCase):
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TestBench = SimBench
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def setUp(self):
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self.tb = self.TestBench()
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def test_to_verilog(self):
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verilog.convert(self.tb)
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def run_with(self, cb, cycles=-1):
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self.tb.callback = cb
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with Simulator(self.tb) as s:
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s.run(cycles)
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