198 lines
6.2 KiB
Python
198 lines
6.2 KiB
Python
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from migen.fhdl.std import *
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from migen.actorlib.structuring import *
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from migen.genlib.fsm import FSM, NextState
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from migen.genlib.misc import chooser
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from misoclib.com.litepcie.core.packet.common import *
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from misoclib.com.litepcie.core.switch.arbiter import Arbiter
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def _encode_header(h_dict, h_signal, obj):
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r = []
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for k, v in sorted(h_dict.items()):
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start = v.word*32+v.offset
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end = start+v.width
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r.append(h_signal[start:end].eq(getattr(obj, k)))
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return r
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class HeaderInserter(Module):
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def __init__(self, dw):
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self.sink = sink = Sink(tlp_raw_layout(dw))
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self.source = source = Source(phy_layout(dw))
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###
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fsm = FSM(reset_state="HEADER1")
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self.submodules += fsm
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sink_dat_r = Signal(dw)
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sink_eop_r = Signal()
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self.sync += \
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If(sink.stb & sink.ack,
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sink_dat_r.eq(sink.dat),
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sink_eop_r.eq(sink.eop)
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)
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fsm.act("HEADER1",
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sink.ack.eq(1),
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If(sink.stb & sink.sop,
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sink.ack.eq(0),
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source.stb.eq(1),
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source.sop.eq(1),
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source.eop.eq(0),
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source.dat.eq(sink.header[:64]),
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source.be.eq(0xff),
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If(source.stb & source.ack,
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NextState("HEADER2"),
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)
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)
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)
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fsm.act("HEADER2",
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source.stb.eq(1),
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source.sop.eq(0),
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source.eop.eq(sink.eop),
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source.dat.eq(Cat(sink.header[64:96], reverse_bytes(sink.dat[:32]))),
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source.be.eq(Cat(Signal(4, reset=0xf), reverse_bits(sink.be[:4]))),
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If(source.stb & source.ack,
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sink.ack.eq(1),
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If(source.eop,
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NextState("HEADER1")
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).Else(
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NextState("COPY")
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)
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)
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)
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fsm.act("COPY",
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source.stb.eq(sink.stb | sink_eop_r),
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source.sop.eq(0),
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source.eop.eq(sink_eop_r),
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source.dat.eq(Cat(reverse_bytes(sink_dat_r[32:64]), reverse_bytes(sink.dat[:32]))),
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If(sink_eop_r,
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source.be.eq(0x0f)
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).Else(
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source.be.eq(0xff)
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),
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If(source.stb & source.ack,
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sink.ack.eq(~sink_eop_r),
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If(source.eop,
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NextState("HEADER1")
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)
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)
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)
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class Packetizer(Module):
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def __init__(self, dw):
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self.req_sink = req_sink = Sink(request_layout(dw))
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self.cmp_sink = cmp_sink = Sink(completion_layout(dw))
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self.source = Source(phy_layout(dw))
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###
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# format TLP request and encode it
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tlp_req = Sink(tlp_request_layout(dw))
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self.comb += [
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tlp_req.stb.eq(req_sink.stb),
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req_sink.ack.eq(tlp_req.ack),
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tlp_req.sop.eq(req_sink.sop),
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tlp_req.eop.eq(req_sink.eop),
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If(req_sink.we,
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Cat(tlp_req.type, tlp_req.fmt).eq(fmt_type_dict["mem_wr32"])
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).Else(
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Cat(tlp_req.type, tlp_req.fmt).eq(fmt_type_dict["mem_rd32"])
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),
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tlp_req.tc.eq(0),
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tlp_req.td.eq(0),
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tlp_req.ep.eq(0),
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tlp_req.attr.eq(0),
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tlp_req.length.eq(req_sink.len),
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tlp_req.requester_id.eq(req_sink.req_id),
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tlp_req.tag.eq(req_sink.tag),
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If(req_sink.len > 1,
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tlp_req.last_be.eq(0xf)
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).Else(
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tlp_req.last_be.eq(0x0)
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),
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tlp_req.first_be.eq(0xf),
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tlp_req.address.eq(req_sink.adr[2:]),
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tlp_req.dat.eq(req_sink.dat),
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If(req_sink.we,
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tlp_req.be.eq(0xff)
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).Else(
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tlp_req.be.eq(0x00)
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),
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]
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tlp_raw_req = Sink(tlp_raw_layout(dw))
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self.comb += [
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tlp_raw_req.stb.eq(tlp_req.stb),
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tlp_req.ack.eq(tlp_raw_req.ack),
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tlp_raw_req.sop.eq(tlp_req.sop),
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tlp_raw_req.eop.eq(tlp_req.eop),
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_encode_header(tlp_request_header, tlp_raw_req.header, tlp_req),
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tlp_raw_req.dat.eq(tlp_req.dat),
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tlp_raw_req.be.eq(tlp_req.be),
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]
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# format TLP completion and encode it
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tlp_cmp = Sink(tlp_completion_layout(dw))
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self.comb += [
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tlp_cmp.stb.eq(cmp_sink.stb),
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cmp_sink.ack.eq(tlp_cmp.ack),
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tlp_cmp.sop.eq(cmp_sink.sop),
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tlp_cmp.eop.eq(cmp_sink.eop),
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tlp_cmp.tc.eq(0),
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tlp_cmp.td.eq(0),
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tlp_cmp.ep.eq(0),
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tlp_cmp.attr.eq(0),
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tlp_cmp.length.eq(cmp_sink.len),
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tlp_cmp.completer_id.eq(cmp_sink.cmp_id),
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If(cmp_sink.err,
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Cat(tlp_cmp.type, tlp_cmp.fmt).eq(fmt_type_dict["cpl"]),
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tlp_cmp.status.eq(cpl_dict["ur"])
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).Else(
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Cat(tlp_cmp.type, tlp_cmp.fmt).eq(fmt_type_dict["cpld"]),
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tlp_cmp.status.eq(cpl_dict["sc"])
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),
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tlp_cmp.bcm.eq(0),
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tlp_cmp.byte_count.eq(cmp_sink.len*4),
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tlp_cmp.requester_id.eq(cmp_sink.req_id),
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tlp_cmp.tag.eq(cmp_sink.tag),
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tlp_cmp.lower_address.eq(cmp_sink.adr),
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tlp_cmp.dat.eq(cmp_sink.dat),
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tlp_cmp.be.eq(0xff)
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]
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tlp_raw_cmp = Sink(tlp_raw_layout(dw))
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self.comb += [
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tlp_raw_cmp.stb.eq(tlp_cmp.stb),
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tlp_cmp.ack.eq(tlp_raw_cmp.ack),
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tlp_raw_cmp.sop.eq(tlp_cmp.sop),
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tlp_raw_cmp.eop.eq(tlp_cmp.eop),
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_encode_header(tlp_completion_header, tlp_raw_cmp.header, tlp_cmp),
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tlp_raw_cmp.dat.eq(tlp_cmp.dat),
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tlp_raw_cmp.be.eq(tlp_cmp.be),
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]
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# arbitrate
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tlp_raw = Sink(tlp_raw_layout(dw))
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self.submodules.arbitrer = Arbiter([tlp_raw_req, tlp_raw_cmp], tlp_raw)
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# insert header
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header_inserter = HeaderInserter(dw)
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self.submodules += header_inserter
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self.comb += [
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Record.connect(tlp_raw, header_inserter.sink),
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Record.connect(header_inserter.source, self.source)
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]
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