litex/examples/basic/tristate.py

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2013-02-14 18:17:24 -05:00
from migen.fhdl.structure import *
from migen.fhdl import verilog
n = 6
pad = Signal(n)
o = Signal(n)
oe = Signal()
i = Signal(n)
f = Fragment(tristates={Tristate(pad, o, oe, i)})
print(verilog.convert(f, ios={pad, o, oe, i}))