2012-03-23 11:41:30 -04:00
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# Copyright (C) 2012 Vermeer Manufacturing Co.
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# License: GPLv3 with additional permissions (see README).
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2012-03-06 13:29:39 -05:00
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from migen.fhdl.structure import *
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2012-03-08 09:55:02 -05:00
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from migen.sim.generic import Simulator
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2012-03-06 13:29:39 -05:00
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class Mem:
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def __init__(self):
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2012-03-10 13:38:39 -05:00
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# Initialize the beginning of the memory with integers
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# from 0 to 19.
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2012-11-26 12:19:10 -05:00
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self.mem = Memory(16, 2**12, init=list(range(20)))
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2012-03-06 13:29:39 -05:00
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def do_simulation(self, s):
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2012-03-10 13:38:39 -05:00
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# Read the memory. Use the cycle counter as address.
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2012-03-06 13:43:59 -05:00
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value = s.rd(self.mem, s.cycle_counter)
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2012-03-10 13:38:39 -05:00
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# Print the result. Output is:
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# 0
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# 1
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# 2
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# ...
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2012-03-06 13:43:59 -05:00
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print(value)
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2012-03-10 13:38:39 -05:00
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# Demonstrate how to interrupt the simulator.
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2012-03-06 13:43:59 -05:00
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if value == 10:
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s.interrupt = True
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2012-03-06 13:29:39 -05:00
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def get_fragment(self):
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return Fragment(memories=[self.mem], sim=[self.do_simulation])
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def main():
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dut = Mem()
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2013-02-09 11:04:53 -05:00
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sim = Simulator(dut.get_fragment())
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2012-03-10 13:38:39 -05:00
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# No need for a cycle limit here, we use sim.interrupt instead.
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2012-03-06 13:29:39 -05:00
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sim.run()
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main()
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