2013-03-10 14:32:38 -04:00
|
|
|
import re
|
|
|
|
|
2012-05-16 19:41:41 -04:00
|
|
|
from migen.fhdl.structure import *
|
2013-03-10 14:32:38 -04:00
|
|
|
from migen.fhdl.module import Module
|
2012-05-16 19:41:41 -04:00
|
|
|
from migen.bank.description import *
|
|
|
|
|
|
|
|
def encode_version(version):
|
|
|
|
match = re.match("(\d+)\.(\d+)(\.(\d+))?(rc(\d+))?", version, re.IGNORECASE)
|
|
|
|
r = (int(match.group(1)) << 12) | (int(match.group(2)) << 8)
|
|
|
|
subminor = match.group(4)
|
|
|
|
rc = match.group(6)
|
|
|
|
if subminor:
|
|
|
|
r |= int(subminor) << 4
|
|
|
|
if rc:
|
|
|
|
r |= int(rc)
|
|
|
|
return r
|
|
|
|
|
2013-03-10 14:32:38 -04:00
|
|
|
class Identifier(Module, AutoReg):
|
|
|
|
def __init__(self, sysid, version, frequency):
|
2013-03-12 10:47:54 -04:00
|
|
|
self._r_sysid = RegisterField(16, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
|
|
|
|
self._r_version = RegisterField(16, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
|
|
|
|
self._r_frequency = RegisterField(32, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
|
2012-05-16 19:41:41 -04:00
|
|
|
|
2013-03-10 14:32:38 -04:00
|
|
|
###
|
|
|
|
|
|
|
|
self.comb += [
|
|
|
|
self._r_sysid.field.w.eq(sysid),
|
|
|
|
self._r_version.field.w.eq(encode_version(version)),
|
|
|
|
self._r_frequency.field.w.eq(frequency)
|
2012-05-16 19:41:41 -04:00
|
|
|
]
|