litex/milkymist/dvisampler/chansync.py

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from migen.fhdl.structure import *
from migen.fhdl.module import Module
from migen.genlib.cdc import MultiReg
from migen.genlib.fifo import SyncFIFO
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from migen.genlib.record import Record
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from migen.genlib.misc import optree
from migen.bank.description import *
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from milkymist.dvisampler.common import channel_layout
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class ChanSync(Module, AutoCSR):
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def __init__(self, nchan=3, depth=8):
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self.valid_i = Signal()
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self.chan_synced = Signal()
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self._r_channels_synced = CSRStatus()
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lst_control_starts = []
all_control_starts = Signal()
for i in range(nchan):
name = "data_in" + str(i)
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data_in = Record(channel_layout, name=name)
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setattr(self, name, data_in)
name = "data_out" + str(i)
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data_out = Record(channel_layout, name=name)
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setattr(self, name, data_out)
###
fifo = SyncFIFO(10, depth)
self.add_submodule(fifo, "pix")
self.comb += [
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fifo.we.eq(self.valid_i),
fifo.din.eq(data_in.raw_bits()),
data_out.raw_bits().eq(fifo.dout)
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]
is_control = Signal()
is_control_r = Signal()
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self.sync.pix += If(fifo.readable & fifo.re, is_control_r.eq(is_control))
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control_starts = Signal()
self.comb += [
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is_control.eq(~data_out.de),
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control_starts.eq(is_control & ~is_control_r),
fifo.re.eq(~is_control | all_control_starts)
]
lst_control_starts.append(control_starts)
some_control_starts = Signal()
self.comb += [
all_control_starts.eq(optree("&", lst_control_starts)),
some_control_starts.eq(optree("|", lst_control_starts))
]
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self.sync.pix += If(~self.valid_i,
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self.chan_synced.eq(0)
).Else(
If(some_control_starts,
If(all_control_starts,
self.chan_synced.eq(1)
).Else(
self.chan_synced.eq(0)
)
)
)
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self.specials += MultiReg(self.chan_synced, self._r_channels_synced.status)