litex/tb/s6ddrphy/Makefile

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Makefile
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2012-02-20 17:55:20 -05:00
SOURCES=tb_s6ddrphy.v ../../verilog/s6ddrphy/s6ddrphy.v \
$(XILINX)/verilog/src/unisims/ODDR2.v \
$(XILINX)/verilog/src/unisims/OSERDES2.v \
$(XILINX)/verilog/src/unisims/ISERDES2.v \
$(XILINX)/verilog/src/unisims/IOBUF.v \
$(XILINX)/verilog/src/unisims/OBUFT.v \
$(XILINX)/verilog/src/unisims/BUFPLL.v
all: tb_s6ddrphy
isim: tb_s6ddrphy
./tb_s6ddrphy
cversim: $(SOURCES)
cver $(SOURCES)
clean:
rm -f tb_s6ddrphy verilog.log s6ddrphy.vcd
tb_s6ddrphy: $(SOURCES)
iverilog -o tb_s6ddrphy $(SOURCES)
.PHONY: clean sim cversim