litex/misoclib/dfii/__init__.py

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from migen.fhdl.std import *
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from migen.bus import dfi
from migen.bank.description import *
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class PhaseInjector(Module, AutoCSR):
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def __init__(self, phase):
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self._command = CSRStorage(6) # cs, we, cas, ras, wren, rden
self._command_issue = CSR()
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self._address = CSRStorage(flen(phase.address))
self._baddress = CSRStorage(flen(phase.bank))
self._wrdata = CSRStorage(flen(phase.wrdata))
self._rddata = CSRStatus(flen(phase.rddata))
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###
self.comb += [
If(self._command_issue.re,
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phase.cs_n.eq(~self._command.storage[0]),
phase.we_n.eq(~self._command.storage[1]),
phase.cas_n.eq(~self._command.storage[2]),
phase.ras_n.eq(~self._command.storage[3])
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).Else(
phase.cs_n.eq(1),
phase.we_n.eq(1),
phase.cas_n.eq(1),
phase.ras_n.eq(1)
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),
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phase.address.eq(self._address.storage),
phase.bank.eq(self._baddress.storage),
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phase.wrdata_en.eq(self._command_issue.re & self._command.storage[4]),
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phase.rddata_en.eq(self._command_issue.re & self._command.storage[5]),
phase.wrdata.eq(self._wrdata.storage),
phase.wrdata_mask.eq(0)
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]
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self.sync += If(phase.rddata_valid, self._rddata.status.eq(phase.rddata))
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class DFIInjector(Module, AutoCSR):
def __init__(self, a, ba, d, nphases=1):
inti = dfi.Interface(a, ba, d, nphases)
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self.slave = dfi.Interface(a, ba, d, nphases)
self.master = dfi.Interface(a, ba, d, nphases)
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self._control = CSRStorage(2) # sel, cke
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for n, phase in enumerate(inti.phases):
setattr(self.submodules, "pi" + str(n), PhaseInjector(phase))
###
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self.comb += If(self._control.storage[0],
self.slave.connect(self.master)
).Else(
inti.connect(self.master)
)
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self.comb += [phase.cke.eq(self._control.storage[1]) for phase in inti.phases]