32 lines
779 B
Python
32 lines
779 B
Python
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from mibuild.generic_platform import *
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from mibuild.crg import SimpleCRG
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from mibuild.sim.verilator import VerilatorPlatform
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class SimPins(Pins):
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def __init__(self, n):
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Pins.__init__(self, "s "*n)
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_io = [
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("sys_clk", 0, SimPins(1)),
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("sys_rst", 0, SimPins(1)),
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("serial", 0,
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Subsignal("source_stb", SimPins(1)),
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Subsignal("source_ack", SimPins(1)),
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Subsignal("source_data", SimPins(8)),
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Subsignal("sink_stb", SimPins(1)),
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Subsignal("sink_ack", SimPins(1)),
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Subsignal("sink_data", SimPins(8)),
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),
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]
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class Platform(VerilatorPlatform):
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is_sim = True
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default_clk_name = "sys_clk"
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default_clk_period = 1000 # on modern computers simulate at ~ 1MHz
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def __init__(self):
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VerilatorPlatform.__init__(self, "SIM", _io)
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def do_finalize(self, fragment):
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pass
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