2012-01-15 16:08:33 -05:00
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from migen.fhdl.structure import *
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from migen.corelogic.record import *
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from migen.corelogic.fsm import *
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from migen.flow.actor import *
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# Generates integers from start to maximum-1
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2012-06-22 09:01:47 -04:00
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class IntSequence(Actor):
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2012-06-17 15:19:47 -04:00
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def __init__(self, nbits, step=1):
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self.nbits = nbits
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2012-01-15 16:08:33 -05:00
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self.step = step
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2012-06-17 15:19:47 -04:00
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2012-06-08 12:06:12 -04:00
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super().__init__(
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2012-06-17 15:19:47 -04:00
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("maximum", Sink, [("value", BV(nbits))]),
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("source", Source, [("value", BV(nbits))]))
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2012-01-15 16:08:33 -05:00
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def get_fragment(self):
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load = Signal()
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ce = Signal()
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last = Signal()
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2012-06-17 15:19:47 -04:00
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maximum = Signal(BV(self.nbits))
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counter = Signal(BV(self.nbits))
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2012-01-15 16:08:33 -05:00
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2012-06-17 15:19:47 -04:00
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if self.step > 1:
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comb = [last.eq(counter + self.step >= maximum)]
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2012-01-15 16:08:33 -05:00
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else:
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2012-06-17 15:19:47 -04:00
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comb = [last.eq(counter + 1 == maximum)]
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2012-01-15 16:08:33 -05:00
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sync = [
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If(load,
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2012-06-17 15:19:47 -04:00
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counter.eq(0),
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maximum.eq(self.token("maximum").value)
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).Elif(ce,
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If(last,
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counter.eq(0)
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).Else(
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counter.eq(counter + self.step)
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)
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)
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2012-01-15 16:08:33 -05:00
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]
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2012-06-17 15:19:47 -04:00
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comb.append(self.token("source").value.eq(counter))
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counter_fragment = Fragment(comb, sync)
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2012-01-15 16:08:33 -05:00
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fsm = FSM("IDLE", "ACTIVE")
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fsm.act(fsm.IDLE,
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load.eq(1),
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2012-06-17 15:19:47 -04:00
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self.endpoints["maximum"].ack.eq(1),
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If(self.endpoints["maximum"].stb, fsm.next_state(fsm.ACTIVE))
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2012-01-15 16:08:33 -05:00
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)
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fsm.act(fsm.ACTIVE,
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self.busy.eq(1),
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self.endpoints["source"].stb.eq(1),
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If(self.endpoints["source"].ack,
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ce.eq(1),
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If(last, fsm.next_state(fsm.IDLE))
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)
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)
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2012-06-17 15:19:47 -04:00
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return counter_fragment + fsm.get_fragment()
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