Initial Efinix Trion support
This commit is contained in:
Franck Jullien
parent
7f8e2e39f3
commit
000aabf85b
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from litex.build.efinix.programmer import EfinixProgrammer
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#
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# This file is part of LiteX.
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#
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# Copyright (c) 2021 Franck Jullien <franck.jullien@collshade.fr>
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# Copyright (c) 2015-2018 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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efinix_special_overrides = {}
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#
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# This file is part of LiteX.
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#
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# Copyright (c) 2021 Franck Jullien <franck.jullien@collshade.fr>
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# Copyright (c) 2015-2018 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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import subprocess
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import pathlib
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import math
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import sys
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import site
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import subprocess
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import inspect
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from lxml import etree
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from litex.build.generic_platform import *
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from migen.fhdl.structure import _Fragment
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from migen.fhdl.tools import *
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from migen.fhdl.namer import build_namespace
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from litex.build.generic_platform import Pins, IOStandard, Misc
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from litex.build import tools
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_reserved_keywords = {
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"always", "and", "assign", "automatic", "begin", "buf", "bufif0", "bufif1",
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"case", "casex", "casez", "cell", "cmos", "config", "deassign", "default",
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"defparam", "design", "disable", "edge", "else", "end", "endcase",
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"endconfig", "endfunction", "endgenerate", "endmodule", "endprimitive",
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"endspecify", "endtable", "endtask", "event", "for", "force", "forever",
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"fork", "function", "generate", "genvar", "highz0", "highz1", "if",
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"ifnone", "incdir", "include", "initial", "inout", "input",
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"instance", "integer", "join", "large", "liblist", "library", "localparam",
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"macromodule", "medium", "module", "nand", "negedge", "nmos", "nor",
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"noshowcancelled", "not", "notif0", "notif1", "or", "output", "parameter",
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"pmos", "posedge", "primitive", "pull0", "pull1" "pulldown",
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"pullup", "pulsestyle_onevent", "pulsestyle_ondetect", "remos", "real",
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"realtime", "reg", "release", "repeat", "rnmos", "rpmos", "rtran",
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"rtranif0", "rtranif1", "scalared", "showcancelled", "signed", "small",
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"specify", "specparam", "strong0", "strong1", "supply0", "supply1",
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"table", "task", "time", "tran", "tranif0", "tranif1", "tri", "tri0",
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"tri1", "triand", "trior", "trireg", "unsigned", "use", "vectored", "wait",
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"wand", "weak0", "weak1", "while", "wire", "wor","xnor", "xor", "do"
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}
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def get_pin_direction(fragment, platform, pinname):
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ios = platform.constraint_manager.get_io_signals()
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sigs = list_signals(fragment) | list_special_ios(fragment, True, True, True)
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special_outs = list_special_ios(fragment, False, True, True)
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inouts = list_special_ios(fragment, False, False, True)
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targets = list_targets(fragment) | special_outs
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ns = build_namespace(list_signals(fragment) \
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| list_special_ios(fragment, True, True, True) \
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| ios, _reserved_keywords)
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ns.clock_domains = fragment.clock_domains
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dir = "Unknown"
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for sig in sorted(ios, key=lambda x: x.duid):
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# Better idea ???
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if (pinname.split('[')[0] == ns.get_name(sig)):
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if sig in inouts:
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dir = "inout"
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elif sig in targets:
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dir = "output"
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else:
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dir = "input"
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return dir
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# Timing Constraints (.sdc) ------------------------------------------------------------------------
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def _build_sdc(clocks, false_paths, vns, named_sc, build_name, additional_sdc_commands):
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sdc = []
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# Clock constraints
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for clk, period in sorted(clocks.items(), key=lambda x: x[0].duid):
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is_port = False
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for sig, pins, others, resname in named_sc:
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if sig == vns.get_name(clk):
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is_port = True
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if is_port:
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tpl = "create_clock -name {clk} -period {period} [get_ports {{{clk}}}]"
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sdc.append(tpl.format(clk=vns.get_name(clk), period=str(period)))
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else:
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tpl = "create_clock -name {clk} -period {period} [get_nets {{{clk}}}]"
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sdc.append(tpl.format(clk=vns.get_name(clk), period=str(period)))
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# False path constraints
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for from_, to in sorted(false_paths, key=lambda x: (x[0].duid, x[1].duid)):
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tpl = "set_false_path -from [get_clocks {{{from_}}}] -to [get_clocks {{{to}}}]"
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sdc.append(tpl.format(from_=vns.get_name(from_), to=vns.get_name(to)))
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# Add additional commands
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sdc += additional_sdc_commands
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# Generate .sdc
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tools.write_to_file("{}.sdc".format(build_name), "\n".join(sdc))
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# Peripheral configuration ------------------------------------------------------------------------
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def _create_gpio_instance(fragment, platform, sig, pins):
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l = ""
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if len(pins) > 1:
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l = ',{},0'.format(len(pins) - 1)
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d = get_pin_direction(fragment, platform, sig)
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return 'design.create_{d}_gpio("{name}"{len})'.format(d =d, name=sig, len=l)
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def _format_constraint(c, signame, fmt_r, fragment, platform):
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# IO location constraints
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if isinstance(c, Pins):
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tpl = 'design.assign_pkg_pin("{signame}","{pin}")\n'
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return tpl.format(signame=signame, name=fmt_r, pin=c.identifiers[0])
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# IO standard property
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elif isinstance(c, IOStandard):
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prop = ""
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valid = ['3.3_V_LVTTL_/_LVCMOS', '2.5_V_LVCMOS', '1.8_V_LVCMOS']
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if c.name in valid:
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prop = 'IO_STANDARD'
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if prop == "":
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print("{} has a wrong IOStandard format [{}]".format(signame, c.name))
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print("Sould be selected from {}\n".format(valid))
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# Print error, warning ??
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return ""
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tpl = 'design.set_property( "{signame}","{prop}","{val}")\n'
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return tpl.format(signame=signame, prop=prop, val=c.name)
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# Others constraints
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elif isinstance(c, Misc):
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prop = ""
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if c.misc in ['WEAK_PULLUP', 'WEAK_PULLDOWN']:
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prop = 'PULL_OPTION'
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val = c.misc
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if 'DRIVE_STRENGTH' in c.misc:
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prop = 'DRIVE_STRENGTH'
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val = c.misc.split('=')[1]
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if prop == "":
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# Print error, warning ??
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return ""
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tpl = 'design.set_property( "{signame}","{prop}","{val}")\n'
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return tpl.format(signame=signame, prop=prop, val=val)
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def _format_conf_constraint(signame, pin, others, resname, fragment, platform):
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fmt_r = "{}:{}".format(*resname[:2])
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if resname[2] is not None:
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fmt_r += "." + resname[2]
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fmt_c = [_format_constraint(c, signame, fmt_r, fragment, platform) for c in ([Pins(pin)] + others)]
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return ''.join(fmt_c)
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def _build_iface_conf(named_sc, named_pc, fragment, platform):
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conf = []
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inst = []
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# GPIO
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for sig, pins, others, resname in named_sc:
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inst.append(_create_gpio_instance(fragment, platform, sig, pins))
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if len(pins) > 1:
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for i, p in enumerate(pins):
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conf.append(_format_conf_constraint("{}[{}]".format(sig, i), p, others, resname, fragment, platform))
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else:
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conf.append(_format_conf_constraint(sig, pins[0], others, resname, fragment, platform))
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if named_pc:
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conf.append("\n\n".join(named_pc))
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# PLL
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#inst.append()
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conf = inst + conf
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return "\n".join(conf)
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def _build_peri(efinity_path, build_name, partnumber, named_sc, named_pc, fragment, platform):
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pythonpath = ""
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header = "# Autogenerated by LiteX / git: " + tools.get_litex_git_revision()
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header += """
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import os
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import sys
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home = '{0}'
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os.environ['EFXPT_HOME'] = home + '/pt'
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os.environ['EFXPGM_HOME'] = home + '/pgm'
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os.environ['EFXDBG_HOME'] = home + '/debugger'
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os.environ['EFXIPM_HOME'] = home + '/ipm'
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sys.path.append(home + '/pt/bin')
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sys.path.append(home + '/lib/python3.8/site-packages')
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from api_service.design import DesignAPI
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from api_service.device import DeviceAPI
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is_verbose = {1}
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design = DesignAPI(is_verbose)
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device = DeviceAPI(is_verbose)
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design.create('{2}', '{3}', './../build', overwrite=True)
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"""
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header = header.format(efinity_path, 'True', build_name, partnumber)
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conf = _build_iface_conf(named_sc, named_pc, fragment, platform)
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footer = """
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# Check design, generate constraints and reports
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#design.generate(enable_bitstream=True)
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# Save the configured periphery design
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design.save()
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"""
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tools.write_to_file("iface.py", header + conf + footer)
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subprocess.call([efinity_path + '/bin/python3', 'iface.py'])
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# Project configuration ------------------------------------------------------------------------
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def _build_xml(name, partnumber, build_name, sources, additional_xml_commands):
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test = '<project xmlns:efx="http://www.efinixinc.com/enf_proj"'
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test += ' xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"'
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test += ' name="{}"'.format(name)
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test += ' description=""'
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test += ' last_change_date="mer. sept. 15 2021 12:04:56"'
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test += ' location="{}"'.format(pathlib.Path().resolve())
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test += ' sw_version="2021.1.165.2.19"'
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test += ' last_run_state="" last_run_tool="" last_run_flow=""'
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test += ' config_result_in_sync="sync" design_ood="sync" place_ood="sync" route_ood="sync"'
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test += ' xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd"'
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test += '/>'
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root = etree.XML(test)
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device_info = etree.SubElement(root, "device_info")
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etree.SubElement(device_info, "family", name = "Trion")
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etree.SubElement(device_info, "device", name = partnumber)
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etree.SubElement(device_info, "timing_model", name = "C4")
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design_info = etree.SubElement(root, "design_info")
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etree.SubElement(design_info, "top_module", name = build_name)
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for filename, language, library in sources:
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val = {'name':filename, 'version':'default', 'library':'default'}
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etree.SubElement(design_info, "design_file", val)
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etree.SubElement(design_info, "top_vhdl_arch", name = "")
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constraint_info = etree.SubElement(root, "constraint_info")
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etree.SubElement(constraint_info, "sdc_file", name = "{}.sdc".format(build_name))
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misc_info = etree.SubElement(root, "misc_info")
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ip_info = etree.SubElement(root, "ip_info")
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synthesis = etree.SubElement(root, "synthesis", tool_name="efx_map")
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for l in additional_xml_commands:
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if l[0] == 'efx_map':
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val = {'name':l[1], 'value':l[2], 'value_type':l[3]}
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etree.SubElement(synthesis, "param", val)
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place_and_route = etree.SubElement(root, "place_and_route", tool_name="efx_pnr")
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for l in additional_xml_commands:
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if l[0] == 'efx_pnr':
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val = {'name':l[1], 'value':l[2], 'value_type':l[3]}
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etree.SubElement(place_and_route, "param", val)
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bitstream_generation = etree.SubElement(root, "bitstream_generation", tool_name="efx_pgm")
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for l in additional_xml_commands:
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if l[0] == 'efx_pgm':
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val = {'name':l[1], 'value':l[2], 'value_type':l[3]}
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etree.SubElement(bitstream_generation, "param", val)
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# Hack
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output = etree.tostring(root, pretty_print=True).decode().replace('<', '<efx:')
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output = output.replace('<efx:/', '</efx:')
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# Generate .xml
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tools.write_to_file("{}.xml".format(build_name), output)
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class EfinityToolchain():
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attr_translate = {}
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def __init__(self, efinity_path):
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self.clocks = dict()
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self.false_paths = set()
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self.efinity_path = efinity_path
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self.additional_sdc_commands = []
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self.additional_xml_commands = []
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def build(self, platform, fragment,
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build_dir = "build",
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build_name = "top",
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run = True,
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**kwargs):
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# Create build directory
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cwd = os.getcwd()
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os.makedirs(build_dir, exist_ok=True)
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os.chdir(build_dir)
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# Finalize design
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if not isinstance(fragment, _Fragment):
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fragment = fragment.get_fragment()
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platform.finalize(fragment)
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# Generate verilog
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v_output = platform.get_verilog(fragment, name=build_name, **kwargs)
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named_sc, named_pc = platform.resolve_signals(v_output.ns)
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v_file = build_name + ".v"
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v_output.write(v_file)
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platform.add_source(v_file)
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if platform.verilog_include_paths:
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self.options['includ_path'] = '{' + ';'.join(platform.verilog_include_paths) + '}'
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os.environ['EFXPT_HOME'] = self.efinity_path + '/pt'
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# Generate design timing constraints file (.sdc)
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_build_sdc(
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clocks = self.clocks,
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false_paths = self.false_paths,
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vns = v_output.ns,
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named_sc = named_sc,
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build_name = build_name,
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additional_sdc_commands = self.additional_sdc_commands)
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# Generate project file (.xml)
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_build_xml(
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name = build_name,
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partnumber = platform.device,
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build_name = build_name,
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sources = platform.sources,
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additional_xml_commands = self.additional_xml_commands)
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# Generate constraints file (.peri.xml)
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_build_peri(
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efinity_path = self.efinity_path,
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build_name = build_name,
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partnumber = platform.device,
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named_sc = named_sc,
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named_pc = named_pc,
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fragment = fragment,
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platform = platform)
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# Run
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if run:
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subprocess.call([self.efinity_path + '/scripts/efx_run.py', build_name + '.xml', '-f', 'compile'])
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os.chdir(cwd)
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return v_output.ns
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def add_period_constraint(self, platform, clk, period):
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clk.attr.add("keep")
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period = math.floor(period*1e3)/1e3 # round to lowest picosecond
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if clk in self.clocks:
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if period != self.clocks[clk]:
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raise ValueError("Clock already constrained to {:.2f}ns, new constraint to {:.2f}ns"
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.format(self.clocks[clk], period))
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self.clocks[clk] = period
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def add_false_path_constraint(self, platform, from_, to):
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from_.attr.add("keep")
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to.attr.add("keep")
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if (to, from_) not in self.false_paths:
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self.false_paths.add((from_, to))
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@ -0,0 +1,52 @@
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#
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# This file is part of LiteX.
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#
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# Copyright (c) 2021 Franck Jullien <franck.jullien@collshade.fr>
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# Copyright (c) 2015-2018 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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from litex.build.generic_platform import GenericPlatform
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from litex.build.efinix import common, efinity
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# EfinixPlatform -----------------------------------------------------------------------------------
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class EfinixPlatform(GenericPlatform):
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bitstream_ext = ".bit"
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def __init__(self, *args, toolchain="efinity", **kwargs):
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GenericPlatform.__init__(self, *args, **kwargs)
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if 'LITEX_ENV_EFINITY' in os.environ:
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self.efinity_path = os.environ['LITEX_ENV_EFINITY'].rstrip('/')
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os.environ['EFINITY_HOME'] = self.efinity_path
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else:
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raise OSError('Unable to find Efinity toolchain, please set LITEX_ENV_EFINITY to ${install_dir}')
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if toolchain == "efinity":
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self.toolchain = efinity.EfinityToolchain(self.efinity_path)
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else:
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raise ValueError("Unknown toolchain")
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def get_verilog(self, *args, special_overrides=dict(), **kwargs):
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so = dict(common.efinix_special_overrides)
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so.update(special_overrides)
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return GenericPlatform.get_verilog(self, *args, special_overrides=so,
|
||||
attr_translate=self.toolchain.attr_translate, **kwargs)
|
||||
|
||||
def build(self, *args, **kwargs):
|
||||
return self.toolchain.build(self, *args, **kwargs)
|
||||
|
||||
def add_period_constraint(self, clk, period):
|
||||
if clk is None: return
|
||||
if hasattr(clk, "p"):
|
||||
clk = clk.p
|
||||
self.toolchain.add_period_constraint(self, clk, period)
|
||||
|
||||
def add_false_path_constraint(self, from_, to):
|
||||
if hasattr(from_, "p"):
|
||||
from_ = from_.p
|
||||
if hasattr(to, "p"):
|
||||
to = to.p
|
||||
self.toolchain.add_false_path_constraint(self, from_, to)
|
||||
|
|
@ -0,0 +1,27 @@
|
|||
#
|
||||
# This file is part of LiteX.
|
||||
#
|
||||
# Copyright (c) 2021 Franck Jullien <franck.jullien@collshade.fr>
|
||||
# SPDX-License-Identifier: BSD-2-Clause
|
||||
|
||||
import os
|
||||
import sys
|
||||
|
||||
from litex.build.generic_programmer import GenericProgrammer
|
||||
|
||||
class EfinixProgrammer(GenericProgrammer):
|
||||
|
||||
def __init__(self, cable_name=""):
|
||||
self.cable_name = cable_name
|
||||
if 'LITEX_ENV_EFINITY' in os.environ:
|
||||
self.efinity_path = os.environ['LITEX_ENV_EFINITY'].rstrip('/')
|
||||
os.environ['EFINITY_HOME'] = self.efinity_path
|
||||
else:
|
||||
raise OSError('Unable to find Efinity toolchain, please set LITEX_ENV_EFINITY to ${install_dir}')
|
||||
|
||||
def load_bitstream(self, bitstream_file, cable_suffix=""):
|
||||
os.environ['EFXPGM_HOME'] = self.efinity_path + '/pgm'
|
||||
self.call([self.efinity_path + '/bin/python3', self.efinity_path +
|
||||
'pgm/bin/efx_pgm/ftdi_program.py', bitstream_file,
|
||||
"-m", "jtag"
|
||||
])
|
||||
Loading…
Reference in New Issue