create Port class and remove connect method of mac/ip/udp Ports

liteeth/common.py

@@ -252,6 +252,15 @@ def eth_etherbone_user_description(dw):
 	return EndpointDescription(payload_layout, param_layout, packetized=True)
 
 
+# Generic classes
+class Port:
+	def connect(self, port):
+		r = [
+			Record.connect(self.source, port.sink),
+			Record.connect(port.source, self.sink)
+		]
+		return r
+
 # Generic modules
 @DecorateModule(InsertReset)
 @DecorateModule(InsertCE)

liteeth/core/ip/common.py

@@ -25,24 +25,12 @@ class LiteEthIPV4MasterPort:
 		self.source = Source(eth_ipv4_user_description(dw))
 		self.sink = Sink(eth_ipv4_user_description(dw))
 
-	def connect(self, slave):
-		return [
-			Record.connect(self.source, slave.sink),
-			Record.connect(slave.source, self.sink)
-		]
-
 class LiteEthIPV4SlavePort:
 	def __init__(self, dw):
 		self.dw = dw
 		self.sink = Sink(eth_ipv4_user_description(dw))
 		self.source = Source(eth_ipv4_user_description(dw))
 
-	def connect(self, master):
-		return [
-			Record.connect(self.sink, master.source),
-			Record.connect(master.sink, self.source)
-		]
-
 class LiteEthIPV4UserPort(LiteEthIPV4SlavePort):
 	def __init__(self, dw):
 		LiteEthIPV4SlavePort.__init__(self, dw)

liteeth/core/udp/common.py

@@ -25,24 +25,12 @@ class LiteEthUDPMasterPort:
 		self.source = Source(eth_udp_user_description(dw))
 		self.sink = Sink(eth_udp_user_description(dw))
 
-	def connect(self, slave):
-		return [
-			Record.connect(self.source, slave.sink),
-			Record.connect(slave.source, self.sink)
-		]
-
 class LiteEthUDPSlavePort:
 	def __init__(self, dw):
 		self.dw =dw
 		self.sink = Sink(eth_udp_user_description(dw))
 		self.source = Source(eth_udp_user_description(dw))
 
-	def connect(self, master):
-		return [
-			Record.connect(self.sink, master.source),
-			Record.connect(master.sink, self.source)
-		]
-
 class LiteEthUDPUserPort(LiteEthUDPSlavePort):
 	def __init__(self, dw):
 		LiteEthUDPSlavePort.__init__(self, dw)

liteeth/mac/__init__.py

@@ -20,10 +20,7 @@ class LiteEthMAC(Module, AutoCSR):
 			]
 		elif interface == "wishbone":
 			self.submodules.interface = LiteEthMACWishboneInterface(dw, 2, 2)
-			self.comb += [
-				Record.connect(self.interface.source, self.core.sink),
-				Record.connect(self.core.source, self.interface.sink)
-			]
+			self.comb += Port.connect(self.interface, self.core)
 			self.ev, self.bus = self.interface.sram.ev, self.interface.bus
 			self.csrs = self.interface.get_csrs()
 		elif interface == "dma":

liteeth/mac/common.py

@@ -24,23 +24,11 @@ class LiteEthMACMasterPort:
 		self.source = Source(eth_mac_description(dw))
 		self.sink = Sink(eth_mac_description(dw))
 
-	def connect(self, slave):
-		return [
-			Record.connect(self.source, slave.sink),
-			Record.connect(slave.source, self.sink)
-		]
-
 class LiteEthMACSlavePort:
 	def __init__(self, dw):
 		self.sink = Sink(eth_mac_description(dw))
 		self.source = Source(eth_mac_description(dw))
 
-	def connect(self, master):
-		return [
-			Record.connect(self.sink, master.source),
-			Record.connect(master.sink, self.source)
-		]
-
 class LiteEthMACUserPort(LiteEthMACSlavePort):
 	def __init__(self, dw):
 		LiteEthMACSlavePort.__init__(self, dw)