Merge pull request #396 from antmicro/external-wb
Add a script that allows to generate standalone cores
This commit is contained in:
enjoy-digital
GitHub
commit
0083e0978b
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@ -1,4 +1,5 @@
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# This file is Copyright (c) 2018-2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# This file is Copyright (c) 2020 Karol Gugala <kgugala@antmicro.com>
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# License: BSD
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"""AXI4 Full/Lite support for LiteX"""
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@ -6,6 +7,7 @@
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from migen import *
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from litex.soc.interconnect import stream
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from litex.build.generic_platform import *
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# AXI Definition -----------------------------------------------------------------------------------
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@ -54,7 +56,7 @@ def r_description(data_width, id_width):
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]
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class AXIInterface(Record):
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def __init__(self, data_width, address_width, id_width=1, clock_domain="sys"):
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def __init__(self, data_width, address_width, mode="master", id_width=1, clock_domain="sys"):
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self.data_width = data_width
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self.address_width = address_width
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self.id_width = id_width
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@ -66,6 +68,80 @@ class AXIInterface(Record):
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self.ar = stream.Endpoint(ax_description(address_width, id_width))
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self.r = stream.Endpoint(r_description(data_width, id_width))
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def _signals_in_channels(self, channels):
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for channel_name in channels:
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channel = getattr(self, channel_name)
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for signal in channel.layout:
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if signal[0] == 'param':
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continue
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if signal[0] == 'payload':
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for s in signal[1]:
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yield s[0], channel_name, s[1], s[2]
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else:
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if signal[0] == 'first':
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continue
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if signal[0] == 'last' and channel_name != 'w' and channel_name != 'r':
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continue
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yield signal[0], channel_name, signal[1], signal[2]
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def to_pads(self, bus_name='axi'):
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axi_bus = {}
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for signal, channel, width, direction in self._signals_in_channels(['aw', 'w', 'b', 'ar', 'r']):
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signal_name = channel + signal
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axi_bus[signal_name] = width
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signals = []
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for pad in axi_bus:
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signals.append(Subsignal(pad, Pins(axi_bus[pad])))
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pads = [
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(bus_name , 0) + tuple(signals)
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]
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return pads
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def connect_to_pads(self, module, platform, bus_name, mode='master'):
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def _get_signals(pads, channel, signal):
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signal_name = channel + signal
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channel = getattr(self, channel)
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axi_signal = getattr(channel, signal)
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pads_signal = getattr(pads, signal_name)
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return pads_signal, axi_signal
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axi_pads = self.to_pads(bus_name)
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platform.add_extension(axi_pads)
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pads = platform.request(bus_name)
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for signal, channel, width, direction in self._signals_in_channels(['aw', 'w', 'ar']):
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pads_signal, axi_signal = _get_signals(pads, channel, signal)
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if mode == 'master':
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if direction == DIR_M_TO_S:
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module.comb += pads_signal.eq(axi_signal)
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else:
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module.comb += axi_signal.eq(pads_signal)
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else:
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if direction == DIR_S_TO_M:
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module.comb += pads_signal.eq(axi_signal)
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else:
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module.comb += axi_signal.eq(pads_signal)
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for signal, channel, width, direction in self._signals_in_channels(['r', 'b']):
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pads_signal, axi_signal = _get_signals(pads, channel, signal)
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if mode == 'master':
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if direction == DIR_S_TO_M:
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module.comb += pads_signal.eq(axi_signal)
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else:
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module.comb += axi_signal.eq(pads_signal)
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else:
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if direction == DIR_M_TO_S:
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module.comb += pads_signal.eq(axi_signal)
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else:
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module.comb += axi_signal.eq(pads_signal)
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# AXI Lite Definition ------------------------------------------------------------------------------
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def ax_lite_description(address_width):
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@ -13,6 +13,7 @@ from migen.genlib.misc import split, displacer, chooser, WaitTimer
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from migen.genlib.fsm import FSM, NextState
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from litex.soc.interconnect import csr
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from litex.build.generic_platform import *
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# TODO: rewrite without FlipFlop
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@ -69,6 +70,59 @@ class Interface(Record):
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yield from self._do_transaction()
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return (yield self.dat_r)
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def _signals_in_channels(self, channels):
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for channel_name in channels:
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s = getattr(self, channel_name)
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for l in _layout:
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if l[0] == channel_name:
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yield channel_name, s.nbits, l[2]
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def to_pads(self, bus_name='wb'):
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wb_bus = {}
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for name, width, direction in self._signals_in_channels(['adr', 'dat_w', 'dat_r',
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'sel', 'cyc', 'stb', 'ack',
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'we', 'cti', 'bte', 'err']):
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signal_name = name
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wb_bus[signal_name] = width
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signals = []
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for pad in wb_bus:
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signals.append(Subsignal(pad, Pins(wb_bus[pad])))
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pads = [
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(bus_name , 0) + tuple(signals)
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]
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print(pads)
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return pads
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def connect_to_pads(self, module, platform, bus_name, mode='master'):
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def _get_signals(pads, name):
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signal_name = name
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wb_signal = getattr(self, signal_name)
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pads_signal = getattr(pads, signal_name)
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return pads_signal, wb_signal
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wb_pads = self.to_pads(bus_name)
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platform.add_extension(wb_pads)
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pads = platform.request(bus_name)
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for name, width, direction in self._signals_in_channels(['adr', 'dat_w', 'dat_r',
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'sel', 'cyc', 'stb', 'ack',
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'we', 'cti', 'bte', 'err']):
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pads_signal, wb_signal = _get_signals(pads, name)
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if mode == 'master':
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if direction == DIR_M_TO_S:
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module.comb += pads_signal.eq(wb_signal)
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else:
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module.comb += wb_signal.eq(pads_signal)
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else:
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if direction == DIR_S_TO_M:
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module.comb += pads_signal.eq(wb_signal)
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else:
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module.comb += wb_signal.eq(pads_signal)
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class InterconnectPointToPoint(Module):
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def __init__(self, master, slave):
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@ -0,0 +1,143 @@
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#!/usr/bin/env python3
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import argparse
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from migen import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.interconnect import wishbone
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from litex.soc.cores.pwm import PWM
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from litex.soc.cores.gpio import GPIOTristate
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from litex.soc.cores.spi import SPIMaster, SPISlave
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from litex.build.generic_platform import *
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class Platform(GenericPlatform):
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def __init__(self, io):
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GenericPlatform.__init__(self, "extractor", io)
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def build(self, fragment, build_dir="build", **kwargs):
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os.makedirs(build_dir, exist_ok=True)
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os.chdir(build_dir)
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top_output = self.get_verilog(fragment)
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top_file = "top.v"
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top_output.write(top_file)
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_io = [
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("sys_clk", 0, Pins(1)),
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("sys_rst", 0, Pins(1)),
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("serial", 0,
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Subsignal("rx", Pins(1)),
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Subsignal("tx", Pins(1)),
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),
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("pwm", 0, Pins(1)),
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]
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class BaseSoC(SoCMini):
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SoCMini.mem_map["csr"] = 0x00000000
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def __init__(self, sys_clk_freq=int(100e6),
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with_pwm=False,
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with_gpio=False, gpio_width=32,
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with_spi_master=False, spi_master_data_width=8, spi_master_clk_freq=8e6,
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**kwargs):
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platform = Platform(_io)
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kwargs["integrated_rom_size"] = 0
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kwargs["integrated_sram_size"] = 0
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# CRG -------------------------------------------------------------------------------------
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self.submodules.crg = CRG(platform.request("sys_clk"), rst=platform.request("sys_rst"))
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# SoCMini ---------------------------------------------------------------------------------
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SoCMini.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
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if with_spi_master:
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platform.add_extension([("spi_m", 0,
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Subsignal("clk", Pins(1)),
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Subsignal("cs_n", Pins(1)),
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Subsignal("mosi", Pins(1)),
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Subsignal("miso", Pins(1)),
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)])
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self.submodules.spi_m = SPIMaster(
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platform.request("spi_m"),
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spi_master_data_width,
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sys_clk_freq,
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spi_master_clk_freq,
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)
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self.add_csr("spi_m")
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if with_pwm:
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self.submodules.pwm = PWM(platform.request("pwm"))
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self.add_csr('pwm')
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if with_gpio:
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platform.add_extension([("gpio", 0, Pins(gpio_width))])
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self.submodules.gpio = GPIOTristate(platform.request("gpio"))
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self.add_csr('gpio')
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self.wb_bus = wishbone.Interface()
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self.bus.add_master(name="wb_master", master=self.wb_bus)
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self.wb_bus.connect_to_pads(self, platform, 'wb', mode='slave')
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for name, loc in sorted(self.irq.locs.items()):
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module = getattr(self, name)
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platform.add_extension([("irq_"+name, 0, Pins(1))])
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irq_pin = platform.request("irq_"+name)
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self.comb += irq_pin.eq(module.ev.irq)
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# Build -------------------------------------------------------------------------------------------
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def soc_argdict(args):
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ret = {}
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for arg in ["with_pwm", "with_uart", "with_ctrl", "with_timer",
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"with_gpio", "gpio_width",
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"with_spi_master", "spi_master_data_width", "spi_master_clk_freq",
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"csr_data_width", "csr_address_width", "csr_paging"]:
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ret[arg] = getattr(args, arg)
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return ret
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC")
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builder_args(parser)
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# Cores
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parser.add_argument("--with-pwm", action="store_true",
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help="Add PWM core")
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parser.add_argument("--with-uart", action="store_true",
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help="Add UART core")
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parser.add_argument("--with-ctrl", action="store_true",
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help="Add bus controller core")
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parser.add_argument("--with-timer", action="store_true",
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help="Add timer core")
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parser.add_argument("--with-spi-master", action="store_true",
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help="Add SPI master core")
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parser.add_argument("--spi-master-data-width", default=8, type=int,
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help="SPI master data width")
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parser.add_argument("--spi-master-clk-freq", default=8e6, type=int,
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help="SPI master output clock frequency")
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parser.add_argument("--with-gpio", action="store_true",
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help="Add GPIO core")
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parser.add_argument("--gpio-width", default=32, type=int,
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help="GPIO signals width")
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# CSR settings
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parser.add_argument("--csr-data-width", default=8, type=int,
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help="CSR bus data-width (8 or 32, default=8)")
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parser.add_argument("--csr-address-width", default=14, type=int,
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help="CSR bus address-width")
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parser.add_argument("--csr-paging", default=0x800, type=int,
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help="CSR bus paging")
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args = parser.parse_args()
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soc = BaseSoC(**soc_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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builder.build()
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if __name__ == "__main__":
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main()
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