Hardware/litex
1
0
Fork 0
mirror of https://github.com/enjoy-digital/litex.git synced 2025-01-04 09:52:26 -05:00
Code Issues Projects Releases Packages Wiki Activity

targets/nexys4ddr: fix typo

Browse source
This commit is contained in:
Florent Kermarrec 2020-01-17 13:17:08 +01:00
parent 36e5274a2b
commit 008a089471
1 changed files with 1 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
litex/boards/targets/nexys4ddr.py
View file

@ -79,7 +79,7 @@ class EthernetSoC(BaseSoC):
# Ethernet ---------------------------------------------------------------------------------
# phy
self.submodules.ethphy = LiteEthPHYMII(
self.submodules.ethphy = LiteEthPHYRMII(
clock_pads = self.platform.request("eth_clocks"),
pads = self.platform.request("eth"))
self.add_csr("ethphy")