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soc_core: update default RocketChip mem_map

This commit is contained in:
Florent Kermarrec 2019-06-28 23:40:01 +02:00
parent 9d170b0944
commit 0116b2b708
1 changed files with 3 additions and 3 deletions
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6
litex/soc/integration/soc_core.py
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@ -186,11 +186,11 @@ class SoCCore(Module):
# Parameters managment --------------------------------------------------------------------- # Parameters managment ---------------------------------------------------------------------
# FIXME: RocketChip reserves the first 256Mbytes for internal use # FIXME: RocketChip reserves the first 256Mbytes for internal use, change default mem_map
# remap rom to 0x10000000, sram to 0x20000000
if cpu_type == "rocket": if cpu_type == "rocket":
self.soc_mem_map["rom"] = 0x10000000 self.soc_mem_map["rom"] = 0x10000000
self.soc_mem_map["sram"] = 0x20000000 self.soc_mem_map["sram"] = 0x11000000
self.soc_mem_map["csr"] = 0x12000000
if cpu_type == "None": if cpu_type == "None":
cpu_type = None cpu_type = None