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soc/cores/dma/WishboneDMAReader: Split add_csr() in add_ctrl() /add_csr() since in some case just want to control the module from signals/user logic.

This commit is contained in:
Florent Kermarrec 2024-06-26 16:13:45 +02:00
parent 23a0d8fa2a
commit 01a15e4bbf
1 changed files with 35 additions and 13 deletions
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48
litex/soc/cores/dma.py
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@ -173,18 +173,19 @@ class WishboneDMAWriter(LiteXModule):
# CSRs. # CSRs.
if with_csr: if with_csr:
self.add_ctrl()
self.add_csr() self.add_csr()
def add_csr(self, default_base=0, default_length=0, default_enable=0, default_loop=0, ready_on_idle=1): def add_ctrl(self, ready_on_idle=1):
self._sink = self.sink self._sink = self.sink
self.sink = stream.Endpoint([("data", self.bus.data_width)]) self.sink = stream.Endpoint([("data", self.bus.data_width)])
self._base = CSRStorage(64, reset=default_base) self.base = Signal(64)
self._length = CSRStorage(32, reset=default_length) self.length = Signal(32)
self._enable = CSRStorage(reset=default_enable) self.enable = Signal()
self._done = CSRStatus() self.done = Signal()
self._loop = CSRStorage(reset=default_loop) self.loop = Signal()
self._offset = CSRStatus(32) self.offset = Signal(32)
# # # # # #
@ -192,13 +193,13 @@ class WishboneDMAWriter(LiteXModule):
base = Signal(self.bus.adr_width) base = Signal(self.bus.adr_width)
offset = Signal(self.bus.adr_width) offset = Signal(self.bus.adr_width)
length = Signal(self.bus.adr_width) length = Signal(self.bus.adr_width)
self.comb += base.eq(self._base.storage[shift:]) self.comb += base.eq(self.base[shift:])
self.comb += length.eq(self._length.storage[shift:]) self.comb += length.eq(self.length[shift:])
self.comb += self._offset.status.eq(offset) self.comb += self.offset.eq(offset)
self.fsm = fsm = ResetInserter()(FSM(reset_state="IDLE")) self.fsm = fsm = ResetInserter()(FSM(reset_state="IDLE"))
self.comb += fsm.reset.eq(~self._enable.storage) self.comb += fsm.reset.eq(~self.enable)
fsm.act("IDLE", fsm.act("IDLE",
self.sink.ready.eq(ready_on_idle), self.sink.ready.eq(ready_on_idle),
NextValue(offset, 0), NextValue(offset, 0),
@ -213,7 +214,7 @@ class WishboneDMAWriter(LiteXModule):
If(self.sink.valid & self.sink.ready, If(self.sink.valid & self.sink.ready,
NextValue(offset, offset + 1), NextValue(offset, offset + 1),
If(self._sink.last, If(self._sink.last,
If(self._loop.storage, If(self.loop,
NextValue(offset, 0) NextValue(offset, 0)
).Else( ).Else(
NextState("DONE") NextState("DONE")
@ -221,4 +222,25 @@ class WishboneDMAWriter(LiteXModule):
) )
) )
) )
fsm.act("DONE", self._done.status.eq(1)) fsm.act("DONE", self.done.eq(1))
def add_csr(self, default_base=0, default_length=0, default_enable=0, default_loop=0):
self._base = CSRStorage(64, reset=default_base)
self._length = CSRStorage(32, reset=default_length)
self._enable = CSRStorage(reset=default_enable)
self._done = CSRStatus()
self._loop = CSRStorage(reset=default_loop)
self._offset = CSRStatus(32)
# # #
self.comb += [
# Control.
self.base.eq(self._base.storage),
self.length.eq(self._length.storage),
self.enable.eq(self._enable.storage),
self.loop.eq(self._loop.storage),
# Status.
self._done.status.eq(self.done),
self._offset.status.eq(self.offset),
]