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integration/soc/usb_acm: run USB ACM in sys_usb clock domain similar to sys clock domain but with rst disconnected.
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1 changed files with 3 additions and 1 deletions
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@ -1141,7 +1141,9 @@ class LiteXSoC(SoC):
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import valentyusb.usbcore.cpu.cdc_eptri as cdc_eptri
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import valentyusb.usbcore.cpu.cdc_eptri as cdc_eptri
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usb_pads = self.platform.request("usb")
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usb_pads = self.platform.request("usb")
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usb_iobuf = usbio.IoBuf(usb_pads.d_p, usb_pads.d_n, usb_pads.pullup)
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usb_iobuf = usbio.IoBuf(usb_pads.d_p, usb_pads.d_n, usb_pads.pullup)
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self.submodules.uart = cdc_eptri.CDCUsb(usb_iobuf)
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self.clock_domains.cd_sys_usb = ClockDomain() # Run USB ACM in sys_usb clock domain similar to
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self.comb += self.cd_sys_usb.clk.eq(ClockSignal("sys")) # sys clock domain but with rst disconnected.
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self.submodules.uart = ClockDomainsRenamer("sys_usb")(cdc_eptri.CDCUsb(usb_iobuf))
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# Classic UART
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# Classic UART
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else:
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else:
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