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soc_core/get_mem_data: add endianness support and use it in builder/initialize_rom to avoid duplication

This commit is contained in:
Florent Kermarrec 2018-09-24 08:01:32 +02:00
parent b528a005a0
commit 01b025aafd
2 changed files with 9 additions and 17 deletions
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19
litex/soc/integration/builder.py
View File

@ -4,7 +4,7 @@ import struct
import shutil
from litex.build.tools import write_to_file
from litex.soc.integration import cpu_interface, soc_sdram
from litex.soc.integration import cpu_interface, soc_core, soc_sdram
from litedram import sdram_init
@ -134,20 +134,9 @@ class Builder:
subprocess.check_call(["make", "-C", dst_dir, "-f", makefile])
def _initialize_rom(self):
bios_file = os.path.join(self.output_dir, "software", "bios",
"bios.bin")
endianness = self.soc.cpu_or_bridge.endianness
with open(bios_file, "rb") as boot_file:
boot_data = []
while True:
w = boot_file.read(4)
if not w:
break
if endianness == 'little':
boot_data.append(struct.unpack("<I", w)[0])
else:
boot_data.append(struct.unpack(">I", w)[0])
self.soc.initialize_rom(boot_data)
bios_file = os.path.join(self.output_dir, "software", "bios","bios.bin")
bios_data = soc_core.get_mem_data(bios_file, self.soc.cpu_or_bridge.endianness)
self.soc.initialize_rom(bios_data)
def build(self, toolchain_path=None, **kwargs):
self.soc.finalize()

7
litex/soc/integration/soc_core.py
View File

@ -28,14 +28,17 @@ def mem_decoder(address, start=26, end=29):
return lambda a: a[start:end] == ((address >> (start+2)) & (2**(end-start))-1)
def get_mem_data(filename, mem_size=None):
def get_mem_data(filename, endianness="big", mem_size=None):
data = []
with open(filename, "rb") as mem_file:
while True:
w = mem_file.read(4)
if not w:
break
data.append(struct.unpack(">I", w)[0])
if endianness == "little":
data.append(struct.unpack("<I", w)[0])
else:
data.append(struct.unpack(">I", w)[0])
data_size = len(data)*4
assert data_size > 0
if mem_size is not None: