Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

reset and lock of PLL OK. We see OOB signals on the link but they are not decoded by the device.

This commit is contained in:
Florent Kermarrec 2014-09-26 21:52:32 +02:00
parent dfbec91a62
commit 01da43ecb2
3 changed files with 19 additions and 18 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
lib/sata/k7sataphy/__init__.py
View File

@ -14,10 +14,8 @@ class K7SATAPHY(Module):
gtx = K7SATAPHYGTX(pads, "SATA3")
self.comb += [
#gtx.rxrate.eq(0b001),
#gtx.txrate.eq(0b001),
gtx.rxrate.eq(0b0),
gtx.txrate.eq(0b0),
gtx.rxrate.eq(0b000),
gtx.txrate.eq(0b000),
]
clocking = K7SATAPHYClocking(pads, gtx)
rxalign = K7SATAPHYRXAlign()

17
lib/sata/k7sataphy/clocking.py
View File

@ -25,7 +25,7 @@ class K7SATAPHYReconfig(Module):
class K7SATAPHYClocking(Module):
def __init__(self, pads, gtx):
self.reset = Signal()
self.transceiver_reset = Signal()
self.gtx_reset = Signal()
self.clock_domains.cd_sata = ClockDomain()
self.clock_domains.cd_sata_tx = ClockDomain()
@ -71,10 +71,14 @@ class K7SATAPHYClocking(Module):
Instance("BUFG", i_I=mmcm_clk0_o, o_O=self.cd_sata_tx.clk),
Instance("BUFG", i_I=mmcm_clk1_o, o_O=self.cd_sata.clk),
]
self.comb += [
gtx.txusrclk.eq(self.cd_sata_tx.clk),
gtx.txusrclk2.eq(self.cd_sata_tx.clk)
]
# RX clocking
self.specials += [
Instance("BUFG", i_I=gtx.rxoutclk, o_O=self.cd_sata_rx.clk),
Instance("BUFG", i_I=mmcm_clk0_o, o_O=self.cd_sata_rx.clk),
]
self.comb += [
gtx.rxusrclk.eq(self.cd_sata_rx.clk),
@ -111,7 +115,8 @@ class K7SATAPHYClocking(Module):
]
# wait till CDR is locked
cdr_cnt = Signal(14, reset=0b10011100010000)
# cdr_cnt = Signal(14, reset=0b10011100010000)
cdr_cnt = Signal(14, reset=1024)
cdr_locked = Signal()
self.sync += \
If(cdr_cnt != 0,
@ -147,11 +152,11 @@ class K7SATAPHYClocking(Module):
gtx.rxuserrdy.eq(gtx.cplllock),
gtx.txuserrdy.eq(gtx.cplllock),
# TX
gtx.gttxreset.eq(rst_cnt_done & (self.reset | self.transceiver_reset | ~gtx.cplllock)),
gtx.gttxreset.eq(rst_cnt_done & (self.reset | self.gtx_reset | ~gtx.cplllock )),
# RX
gtx.gtrxreset.eq(rst_cnt_done & (self.reset | self.transceiver_reset | ~gtx.cplllock)),
gtx.gtrxreset.eq(rst_cnt_done & (self.reset | self.gtx_reset | ~gtx.cplllock)),
# PLL
gtx.cpllreset.eq(rst_cnt_done & self.reset)
gtx.cpllreset.eq(rst_cnt_done & (self.reset | ~cdr_locked))
]
# SATA TX/RX clock domains
self.specials += [

14
lib/sata/k7sataphy/gtx.py
View File

@ -82,8 +82,6 @@ class K7SATAPHYGTX(Module):
# Transmit Ports - TX Data Path interface
self.gttxreset = Signal()
self.txpcsreset = Signal()
self.txpmareset = Signal()
self.txdata = Signal()
self.txoutclk = Signal()
self.txoutclkfabric = Signal()
@ -130,7 +128,7 @@ class K7SATAPHYGTX(Module):
"p_SIM_TX_EIDLE_DRIVE_LEVEL":"X",
"p_SIM_RESET_SPEEDUP":"TRUE",
"p_SIM_CPLLREFCLK_SEL":0b001,
"p_SIM_VERSION":"3.0",
"p_SIM_VERSION":"4.0",
# RX Byte and Word Alignment Attributes
"p_ALIGN_COMMA_DOUBLE":"FALSE",
@ -140,9 +138,9 @@ class K7SATAPHYGTX(Module):
"p_ALIGN_MCOMMA_VALUE":K28_5,
"p_ALIGN_PCOMMA_DET":"TRUE",
"p_ALIGN_PCOMMA_VALUE":~K28_5,
"p_SHOW_REALIGN_COMMA":"TRUE",
"p_SHOW_REALIGN_COMMA":"FALSE",
"p_RXSLIDE_AUTO_WAIT":7,
"p_RXSLIDE_MODE":"PCS",
"p_RXSLIDE_MODE":"OFF",
"p_RX_SIG_VALID_DLY":10,
# RX 8B/10B Decoder Attributes
@ -305,7 +303,7 @@ class K7SATAPHYGTX(Module):
# TX Buffer Attributes
"p_TXBUF_EN":"FALSE",
"p_TXBUF_RESET_ON_RATE_CHANGE":"TRUE",
"p_TXBUF_RESET_ON_RATE_CHANGE":"FALSE",
"p_TXDLY_CFG":0x1f,
"p_TXDLY_LCFG":0x030,
"p_TXDLY_TAP_CFG":0,
@ -732,8 +730,8 @@ class K7SATAPHYGTX(Module):
i_TXSTARTSEQ=0,
# Transmit Ports - TX Initialization and Reset Ports
i_TXPCSRESET=self.txpcsreset,
i_TXPMARESET=self.txpmareset,
i_TXPCSRESET=0,
i_TXPMARESET=0,
o_TXRESETDONE=self.txresetdone,
# Transmit Ports - TX OOB signalling Ports