Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

targets: rename gateware-toolchain parameter to toolchain.

This commit is contained in:
Florent Kermarrec 2020-06-02 13:44:23 +02:00
parent 245985d6c5
commit 01f7947b56
3 changed files with 5 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
litex/boards/targets/simple.py
View File

@ -47,12 +47,12 @@ def main():
soc_core_args(parser) soc_core_args(parser)
parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
parser.add_argument("platform", help="Module name of the platform to build for") parser.add_argument("platform", help="Module name of the platform to build for")
parser.add_argument("--gateware-toolchain", default=None, help="FPGA gateware toolchain used for build") parser.add_argument("--toolchain", default=None, help="FPGA gateware toolchain used for build")
args = parser.parse_args() args = parser.parse_args()
platform_module = importlib.import_module(args.platform) platform_module = importlib.import_module(args.platform)
if args.gateware_toolchain is not None: if args.toolchain is not None:
platform = platform_module.Platform(toolchain=args.gateware_toolchain) platform = platform_module.Platform(toolchain=args.toolchain)
else: else:
platform = platform_module.Platform() platform = platform_module.Platform()
soc = BaseSoC(platform, with_ethernet=args.with_ethernet, **soc_core_argdict(args)) soc = BaseSoC(platform, with_ethernet=args.with_ethernet, **soc_core_argdict(args))

2
litex/boards/targets/ulx3s.py
View File

@ -102,7 +102,7 @@ def main():
parser = argparse.ArgumentParser(description="LiteX SoC on ULX3S") parser = argparse.ArgumentParser(description="LiteX SoC on ULX3S")
parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--gateware-toolchain", dest="toolchain", default="trellis", help="Gateware toolchain to use, trellis (default) or diamond") parser.add_argument("--toolchain", default="trellis", help="Gateware toolchain to use, trellis (default) or diamond")
parser.add_argument("--device", dest="device", default="LFE5U-45F", help="FPGA device, ULX3S can be populated with LFE5U-45F (default) or LFE5U-85F") parser.add_argument("--device", dest="device", default="LFE5U-45F", help="FPGA device, ULX3S can be populated with LFE5U-45F (default) or LFE5U-85F")
parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency (default=50MHz)") parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency (default=50MHz)")
parser.add_argument("--sdram-module", default="MT48LC16M16", help="SDRAM module: MT48LC16M16, AS4C32M16 or AS4C16M16 (default=MT48LC16M16)") parser.add_argument("--sdram-module", default="MT48LC16M16", help="SDRAM module: MT48LC16M16, AS4C32M16 or AS4C16M16 (default=MT48LC16M16)")

2
litex/boards/targets/versa_ecp5.py
View File

@ -119,7 +119,7 @@ def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Versa ECP5") parser = argparse.ArgumentParser(description="LiteX SoC on Versa ECP5")
parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--gateware-toolchain", dest="toolchain", default="trellis", help="Gateware toolchain to use, trellis (default) or diamond") parser.add_argument("--toolchain", default="trellis", help="Gateware toolchain to use, trellis (default) or diamond")
builder_args(parser) builder_args(parser)
soc_sdram_args(parser) soc_sdram_args(parser)
trellis_args(parser) trellis_args(parser)