Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

integration/soc/add_sdcard: always use 32-bit/512bytes memories (not sure this will change?) and allocate sdwrite/sdread regions dynamically.

This commit is contained in:
Florent Kermarrec 2020-05-27 23:26:26 +02:00
parent 4b3afa75a7
commit 02072deab1
2 changed files with 9 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
litex/boards/targets/nexys4ddr.py
View File

@ -47,10 +47,6 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------ # BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore): class BaseSoC(SoCCore):
mem_map = {**SoCCore.mem_map, **{
"sdread": 0x80002000, # len: 0x200
"sdwrite": 0x80002200, # len: 0x200
}}
def __init__(self, sys_clk_freq=int(75e6), with_ethernet=False, **kwargs): def __init__(self, sys_clk_freq=int(75e6), with_ethernet=False, **kwargs):
platform = nexys4ddr.Platform() platform = nexys4ddr.Platform()

19
litex/soc/integration/soc.py
View File

@ -1243,14 +1243,16 @@ class LiteXSoC(SoC):
self.add_csr(name) self.add_csr(name)
# Add SDCard ----------------------------------------------------------------------------------- # Add SDCard -----------------------------------------------------------------------------------
def add_sdcard(self, name="sdcard", memory_size=512, memory_width=32): def add_sdcard(self, name="sdcard"):
assert self.platform.device[:3] == "xc7" # FIXME: Only supports 7-Series for now. assert self.platform.device[:3] == "xc7" # FIXME: Only supports 7-Series for now.
# Imports # Imports
from litesdcard.phy import SDPHY from litesdcard.phy import SDPHY
from litesdcard.clocker import SDClockerS7 from litesdcard.clocker import SDClockerS7
from litesdcard.core import SDCore from litesdcard.core import SDCore
from litesdcard.bist import BISTBlockGenerator, BISTBlockChecker from litesdcard.bist import BISTBlockGenerator, BISTBlockChecker
from litesdcard.data import SDDataReader, SDDataWriter from litesdcard.data import SDDataReader, SDDataWriter
# Core # Core
sdcard_pads = self.platform.request(name) sdcard_pads = self.platform.request(name)
if hasattr(sdcard_pads, "rst"): if hasattr(sdcard_pads, "rst"):
@ -1265,26 +1267,22 @@ class LiteXSoC(SoC):
self.add_csr("sdtimer") self.add_csr("sdtimer")
# SD Card Data Reader # SD Card Data Reader
sdread_mem = Memory(memory_width, memory_size//4) sdread_mem = Memory(32, 512//4)
sdread_sram = FullMemoryWE()(wishbone.SRAM(sdread_mem, read_only=True)) sdread_sram = FullMemoryWE()(wishbone.SRAM(sdread_mem, read_only=True))
self.submodules += sdread_sram self.submodules += sdread_sram
self.bus.add_slave("sdread", sdread_sram.bus, SoCRegion(size=512, cached=False))
self.add_wb_slave(self.mem_map["sdread"], sdread_sram.bus, memory_size)
self.add_memory_region("sdread", self.mem_map["sdread"], memory_size)
sdread_port = sdread_sram.mem.get_port(write_capable=True); sdread_port = sdread_sram.mem.get_port(write_capable=True);
self.specials += sdread_port self.specials += sdread_port
self.submodules.sddatareader = SDDataReader(port=sdread_port, endianness=self.cpu.endianness) self.submodules.sddatareader = SDDataReader(port=sdread_port, endianness=self.cpu.endianness)
self.add_csr("sddatareader") self.add_csr("sddatareader")
self.comb += self.sdcore.source.connect(self.sddatareader.sink), self.comb += self.sdcore.source.connect(self.sddatareader.sink)
# SD Card Data Writer # SD Card Data Writer
sdwrite_mem = Memory(memory_width, memory_size//4) sdwrite_mem = Memory(32, 512//4)
sdwrite_sram = FullMemoryWE()(wishbone.SRAM(sdwrite_mem, read_only=False)) sdwrite_sram = FullMemoryWE()(wishbone.SRAM(sdwrite_mem, read_only=False))
self.submodules += sdwrite_sram self.submodules += sdwrite_sram
self.bus.add_slave("sdwrite", sdwrite_sram.bus, SoCRegion(size=512, cached=False))
self.add_wb_slave(self.mem_map["sdwrite"], sdwrite_sram.bus, memory_size)
self.add_memory_region("sdwrite", self.mem_map["sdwrite"], memory_size)
sdwrite_port = sdwrite_sram.mem.get_port(write_capable=False, async_read=True, mode=READ_FIRST); sdwrite_port = sdwrite_sram.mem.get_port(write_capable=False, async_read=True, mode=READ_FIRST);
self.specials += sdwrite_port self.specials += sdwrite_port
@ -1292,6 +1290,7 @@ class LiteXSoC(SoC):
self.add_csr("sddatawriter") self.add_csr("sddatawriter")
self.comb += self.sddatawriter.source.connect(self.sdcore.sink), self.comb += self.sddatawriter.source.connect(self.sdcore.sink),
# Timing constraints
self.platform.add_period_constraint(self.sdclk.cd_sd.clk, 1e9/self.sys_clk_freq) self.platform.add_period_constraint(self.sdclk.cd_sd.clk, 1e9/self.sys_clk_freq)
self.platform.add_period_constraint(self.sdclk.cd_sd_fb.clk, 1e9/self.sys_clk_freq) self.platform.add_period_constraint(self.sdclk.cd_sd_fb.clk, 1e9/self.sys_clk_freq)
self.platform.add_false_path_constraints( self.platform.add_false_path_constraints(