integration/soc: Add check_bios_requirements method and check for ctrl, timer0, rom and sram presence in the SoC when using the BIOS.

litex/soc/integration/builder.py

@@ -258,12 +258,19 @@ class Builder:
         if self.soc.cpu_type is not None:
             if self.soc.cpu.use_rom:
                 # Prepare/Generate ROM software.
+                use_bios = (
+                    # BIOS compilation enabled.
+                    self.compile_software and
+                    # ROM contents has not already been initialized.
+                    (not self.soc.integrated_rom_initialized)
+                )
+                if use_bios:
+                    self.soc.check_bios_requirements()
                 self._prepare_rom_software()
-                self._generate_rom_software(not self.soc.integrated_rom_initialized)
+                self._generate_rom_software(compile_bios=use_bios)
 
                 # Initialize ROM.
-                if self.soc.integrated_rom_size and self.compile_software:
-                    if not self.soc.integrated_rom_initialized:
+                if use_bios and self.soc.integrated_rom_size:
                     self._initialize_rom_software()
 
         # Translate compile_gateware to run.

litex/soc/integration/soc.py

@@ -784,6 +784,25 @@ class SoC(Module):
         else:
             self.add_constant(name, value)
 
+    def check_bios_requirements(self):
+        # Check for required Peripherals.
+        for periph in ["ctrl", "timer0"]:
+            if periph not in self.csr.locs.keys():
+                self.logger.error("BIOS needs {} peripheral to be {}.".format(
+                    colorer(periph),
+                    colorer("used", color="red")))
+                self.logger.error(self.bus)
+                raise
+
+        # Check for required Memory Regions.
+        for mem in ["rom", "sram"]:
+            if mem not in self.bus.regions.keys():
+                self.logger.error("BIOS needs {} Region to be {} as Bus or Linker Region.".format(
+                    colorer(mem),
+                    colorer("defined", color="red")))
+                self.logger.error(self.bus)
+                raise
+
     # SoC Main Components --------------------------------------------------------------------------
     def add_controller(self, name="ctrl", **kwargs):
         self.check_if_exists(name)
@@ -1029,12 +1048,6 @@ class SoC(Module):
 
         # SoC CPU Check ----------------------------------------------------------------------------
         if not isinstance(self.cpu, (cpu.CPUNone, cpu.Zynq7000)):
-            if "sram" not in self.bus.regions.keys():
-                self.logger.error("CPU needs {} Region to be {} as Bus or Linker Region.".format(
-                    colorer("sram"),
-                    colorer("defined", color="red")))
-                self.logger.error(self.bus)
-                raise
             cpu_reset_address_valid = False
             for name, container in self.bus.regions.items():
                 if self.bus.check_region_is_in(