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Naxriscv now scans for executable mem regions and forwards that info to the scala build process 

Format:
--scala-args=executable-region=(origin, length), --scala-args=exe...
This commit is contained in:
Christian Klarhorst 2022-08-30 16:41:39 +02:00
parent 3e42133abd
commit 027306972a
1 changed files with 8 additions and 1 deletions
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9
litex/soc/cores/cpu/naxriscv/core.py
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@ -395,6 +395,7 @@ class NaxRiscv(CPU):
o_peripheral_clint_rresp = clintbus.r.resp, o_peripheral_clint_rresp = clintbus.r.resp,
) )
soc.bus.add_slave("clint", clintbus, region=soc_region_cls(origin=soc.mem_map.get("clint"), size=0x1_0000, cached=False)) soc.bus.add_slave("clint", clintbus, region=soc_region_cls(origin=soc.mem_map.get("clint"), size=0x1_0000, cached=False))
self.soc = soc # Save SoC instance to retrieve the final mem layout on finalization
def add_memory_buses(self, address_width, data_width, accessible_region): def add_memory_buses(self, address_width, data_width, accessible_region):
nax_data_width = 64 nax_data_width = 64
@ -467,8 +468,14 @@ class NaxRiscv(CPU):
def do_finalize(self): def do_finalize(self):
assert hasattr(self, "reset_address") assert hasattr(self, "reset_address")
self.find_scala_files() self.find_scala_files()
# Find mem regions with executable flag
for region in self.soc.bus.regions.values():
if 'x' in region.mode:
self.scala_args.append('executable-region=(0x{region.origin:x},0x{region.size:x})'
.format(region=region))
self.generate_netlist_name(self.reset_address) self.generate_netlist_name(self.reset_address)
# Do verilog instance. # Do verilog instance.