Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Merge pull request #1810 from trabucayre/etherbone_expose_params 

soc/integration/soc: expose interface,endianness and xx_cdc_xx to target (required for hybrid etherbone)
This commit is contained in:
enjoy-digital 2023-10-23 18:41:52 +02:00 committed by GitHub
parent 5a217528a4 bf3286f564
commit 02b16f1f26
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 5 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
litex/soc/integration/soc.py
View File

@ -1732,7 +1732,9 @@ class LiteXSoC(SoC):
udp_port = 1234, udp_port = 1234,
buffer_depth = 16, buffer_depth = 16,
with_ip_broadcast = True, with_ip_broadcast = True,
with_timing_constraints = True): with_timing_constraints = True,
interface = "crossbar",
endianness = "big"):
# Imports # Imports
from liteeth.core import LiteEthUDPIPCore from liteeth.core import LiteEthUDPIPCore
from liteeth.frontend.etherbone import LiteEthEtherbone from liteeth.frontend.etherbone import LiteEthEtherbone
@ -1751,6 +1753,8 @@ class LiteXSoC(SoC):
dw = data_width, dw = data_width,
with_ip_broadcast = with_ip_broadcast, with_ip_broadcast = with_ip_broadcast,
with_sys_datapath = with_sys_datapath, with_sys_datapath = with_sys_datapath,
interface = interface,
endianness = endianness,
) )
if not with_sys_datapath: if not with_sys_datapath:
# Use PHY's eth_tx/eth_rx clock domains. # Use PHY's eth_tx/eth_rx clock domains.