Merge pull request #1810 from trabucayre/etherbone_expose_params

soc/integration/soc: expose interface,endianness and xx_cdc_xx to target (required for hybrid etherbone)
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enjoy-digital 2023-10-23 18:41:52 +02:00 committed by GitHub
commit 02b16f1f26
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1 changed files with 5 additions and 1 deletions

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@ -1732,7 +1732,9 @@ class LiteXSoC(SoC):
udp_port = 1234,
buffer_depth = 16,
with_ip_broadcast = True,
with_timing_constraints = True):
with_timing_constraints = True,
interface = "crossbar",
endianness = "big"):
# Imports
from liteeth.core import LiteEthUDPIPCore
from liteeth.frontend.etherbone import LiteEthEtherbone
@ -1751,6 +1753,8 @@ class LiteXSoC(SoC):
dw = data_width,
with_ip_broadcast = with_ip_broadcast,
with_sys_datapath = with_sys_datapath,
interface = interface,
endianness = endianness,
)
if not with_sys_datapath:
# Use PHY's eth_tx/eth_rx clock domains.