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targets/icebreaker: create CRG after SoC.

This commit is contained in:
Florent Kermarrec 2020-03-10 11:09:56 +01:00
parent ba2f31d43d
commit 02cba41d64
1 changed files with 3 additions and 3 deletions
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6
litex/boards/targets/icebreaker.py
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@ -71,12 +71,12 @@ class BaseSoC(SoCCore):
# Set CPU variant / reset address # Set CPU variant / reset address
kwargs["cpu_reset_address"] = self.mem_map["spiflash"] + bios_flash_offset kwargs["cpu_reset_address"] = self.mem_map["spiflash"] + bios_flash_offset
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# SoCCore ---------------------------------------------------------------------------------- # SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq, **kwargs) SoCCore.__init__(self, platform, sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# 128KB SPRAM (used as SRAM) --------------------------------------------------------------- # 128KB SPRAM (used as SRAM) ---------------------------------------------------------------
self.submodules.spram = Up5kSPRAM(size=64*kB) self.submodules.spram = Up5kSPRAM(size=64*kB)
self.register_mem("sram", self.mem_map["sram"], self.spram.bus, 64*kB) self.register_mem("sram", self.mem_map["sram"], self.spram.bus, 64*kB)