boards/targets/ulx3s: allow running test_targets on it
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5a1925df2e
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02ffbed5e3
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@ -49,7 +49,8 @@ class _CRG(Module):
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# BaseSoC ------------------------------------------------------------------------------------------
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCSDRAM):
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class BaseSoC(SoCSDRAM):
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def __init__(self, platform, **kwargs):
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def __init__(self, device="LFE5U-45F", toolchain="diamond", **kwargs):
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platform = ulx3s.Platform(device=device, toolchain=toolchain)
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sys_clk_freq = int(50e6)
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sys_clk_freq = int(50e6)
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SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
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SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
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integrated_rom_size=0x8000,
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integrated_rom_size=0x8000,
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@ -76,8 +77,7 @@ def main():
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soc_sdram_args(parser)
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soc_sdram_args(parser)
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args = parser.parse_args()
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args = parser.parse_args()
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platform = ulx3s.Platform(device=args.device, toolchain=args.toolchain)
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soc = BaseSoC(args.device, args.toolchain, **soc_sdram_argdict(args))
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soc = BaseSoC(platform, **soc_sdram_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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builder.build()
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builder.build()
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